cvs commit: src/sys/dev/uart uart_dev_ns8250.c

[Thomas Moestl]

tmm         2004/05/26 14:59:01 PDT

  FreeBSD src repository

  Modified files:
    sys/dev/uart         uart_dev_ns8250.c 
  Log:
  It seems that clearing the MCR_IE bit in the modem control register
  does not reliably prevent the triggering of interrupts for all supported
  configurations. Thus, the FIFO size probe could cause an interrupt,
  which could lead to an interrupt storm in the shared interrupt case.
  
  To prevent this, change ns8250_bus_probe() to use the overflow bit in
  the line status register instead of the RX ready bit in the interrupt
  identification register to detect whether the FIFO has filled up.
  This allows us to clear all bits in the interrupt enable register during
  the probe, which should prevent interrupts reliably.
  Additionally, the detected FIFO size may be a bit more accurate, because
  the overflow bit is only set when the FIFO did actually fill up, while
  interrupts would trigger a bit early.
  
  Reviewed and tested on a lot of hardware by:    marcel
  
  Revision  Changes    Path
  1.7       +23 -22    src/sys/dev/uart/uart_dev_ns8250.c