[package - main-amd64-default][devel/lattice-ice40-examples-hx8k] Failed for lattice-ice40-examples-hx8k-g20180310_2 in build
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Date: Thu, 04 Jul 2024 15:28:33 UTC
You are receiving this mail as a port that you maintain
is failing to build on the FreeBSD package build server.
Please investigate the failure and submit a PR to fix
build.
Maintainer: manu@FreeBSD.org
Log URL: https://pkg-status.freebsd.org/beefy18/data/main-amd64-default/p58363a86b3c6_scf2c79915a6/logs/lattice-ice40-examples-hx8k-g20180310_2.log
Build URL: https://pkg-status.freebsd.org/beefy18/build.html?mastername=main-amd64-default&build=p58363a86b3c6_scf2c79915a6
Log:
=>> Building devel/lattice-ice40-examples-hx8k
build started at Thu Jul 4 15:28:09 UTC 2024
port directory: /usr/ports/devel/lattice-ice40-examples-hx8k
package name: lattice-ice40-examples-hx8k-g20180310_2
building for: FreeBSD main-amd64-default-job-12 15.0-CURRENT FreeBSD 15.0-CURRENT 1500019 amd64
maintained by: manu@FreeBSD.org
Makefile datestamp: -rw-r--r-- 1 root wheel 1434 Apr 25 2023 /usr/ports/devel/lattice-ice40-examples-hx8k/Makefile
Ports top last git commit: 58363a86b3c
Ports top unclean checkout: no
Port dir last git commit: 8d3e020ed03
Port dir unclean checkout: no
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Host OSVERSION: 1500019
Jail OSVERSION: 1500019
Job Id: 12
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=======================<phase: check-sanity >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===> License APACHE20 accepted by the user
===========================================================================
=======================<phase: pkg-depends >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===> lattice-ice40-examples-hx8k-g20180310_2 depends on file: /usr/local/sbin/pkg - not found
===> Installing existing package /packages/All/pkg-1.21.3.pkg
[main-amd64-default-job-12] Installing pkg-1.21.3...
[main-amd64-default-job-12] Extracting pkg-1.21.3: .......... done
===> lattice-ice40-examples-hx8k-g20180310_2 depends on file: /usr/local/sbin/pkg - found
===> Returning to build of lattice-ice40-examples-hx8k-g20180310_2
===========================================================================
=======================<phase: fetch-depends >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===========================================================================
=======================<phase: fetch >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===> License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310_2 for building
===========================================================================
=======================<phase: checksum >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===> License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310_2 for building
=> SHA256 Checksum OK for OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz.
===========================================================================
=======================<phase: extract-depends>============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===========================================================================
=======================<phase: extract >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===> License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310_2 for building
===> Extracting for lattice-ice40-examples-hx8k-g20180310_2
=> SHA256 Checksum OK for OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz.
===========================================================================
=======================<phase: patch-depends >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===========================================================================
=======================<phase: patch >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===> Patching for lattice-ice40-examples-hx8k-g20180310_2
===========================================================================
=======================<phase: build-depends >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===> lattice-ice40-examples-hx8k-g20180310_2 depends on executable: abc - not found
===> Installing existing package /packages/All/abc-g20220920.pkg
[main-amd64-default-job-12] Installing abc-g20220920...
[main-amd64-default-job-12] `-- Installing readline-8.2.10...
[main-amd64-default-job-12] | `-- Installing indexinfo-0.3.1...
[main-amd64-default-job-12] | `-- Extracting indexinfo-0.3.1: .... done
[main-amd64-default-job-12] `-- Extracting readline-8.2.10: .......... done
[main-amd64-default-job-12] Extracting abc-g20220920: ..... done
===> lattice-ice40-examples-hx8k-g20180310_2 depends on executable: abc - found
===> Returning to build of lattice-ice40-examples-hx8k-g20180310_2
===> lattice-ice40-examples-hx8k-g20180310_2 depends on executable: arachne-pnr - not found
===> Installing existing package /packages/All/arachne-pnr-g20181021_3.pkg
[main-amd64-default-job-12] Installing arachne-pnr-g20181021_3...
[main-amd64-default-job-12] Extracting arachne-pnr-g20181021_3: ......... done
=====
Message from arachne-pnr-g20181021_3:
--
===> NOTICE:
<snip>
2.43. Executing ICE40_WRAPCARRY pass (wrap carries).
2.44. Executing TECHMAP pass (map to technology primitives).
2.44.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.
2.44.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 19 unused cells and 727 unused wires.
2.45. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs: 60
1-LUT 6
2-LUT 9
3-LUT 42
4-LUT 3
with \SB_CARRY (#0) 36
with \SB_CARRY (#1) 36
Eliminating LUTs.
Number of LUTs: 60
1-LUT 6
2-LUT 9
3-LUT 42
4-LUT 3
with \SB_CARRY (#0) 36
with \SB_CARRY (#1) 36
Combining LUTs.
Number of LUTs: 59
1-LUT 6
2-LUT 8
3-LUT 42
4-LUT 3
with \SB_CARRY (#0) 36
with \SB_CARRY (#1) 36
Eliminated 0 LUTs.
Combined 1 LUTs.
<suppressed ~268 debug messages>
2.46. Executing TECHMAP pass (map to technology primitives).
2.46.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
2.46.2. Continuing TECHMAP pass.
Using template $paramod$d151c38cd9b2f723ca2e7bae80e30ea6d32d7878\$lut for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
No more expansions possible.
<suppressed ~257 debug messages>
Removed 0 unused cells and 123 unused wires.
2.47. Executing AUTONAME pass.
Renamed 973 objects in module top (38 iterations).
<suppressed ~260 debug messages>
2.48. Executing HIERARCHY pass (managing design hierarchy).
2.48.1. Analyzing design hierarchy..
Top module: \top
2.48.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.49. Printing statistics.
=== top ===
Number of wires: 119
Number of wire bits: 170
Number of public wires: 119
Number of public wire bits: 170
Number of ports: 5
Number of port bits: 5
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 157
SB_CARRY 49
SB_DFF 16
SB_DFFE 1
SB_DFFESR 15
SB_DFFESS 1
SB_DFFSR 16
SB_LUT4 59
2.50. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.
2.51. Executing BLIF backend.
End of script. Logfile hash: d909fd0b47, CPU: user 2.45s system 0.02s, MEM: 35.26 MB peak
Yosys 0.42 (git sha1 9b6afcf3f83, c++ 18.1.6 -O2 -fstack-protector-strong -fno-strict-aliasing -fPIC -Os)
Time spent: 55% 21x read_verilog (1 sec), 6% 27x opt_expr (0 sec), ...
arachne-pnr -d 8k -o example.asc -p ice40hx8k-evb.pcf example.blif -P ct256
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif example.blif...
prune...
read_pcf ice40hx8k-evb.pcf...
instantiate_io...
pack...
After packing:
IOs 5 / 206
GBs 0 / 8
GB_IOs 0 / 8
LCs 85 / 7680
DFF 16
CARRY 20
CARRY, DFF 33
DFF PASS 4
CARRY PASS 6
BRAMs 0 / 32
WARMBOOTs 0 / 1
PLLs 0 / 2
place_constraints...
promote_globals...
promoted clk_24KHz, 38 / 38
promoted LED1_m1_r_SB_DFFESS_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O, 17 / 17
promoted BUT2_r_SB_LUT4_I2_O[1], 16 / 17
promoted reset_SB_LUT4_I2_1_O, 14 / 14
promoted CLK$2, 12 / 12
promoted 5 nets
2 sr/we
1 cen/wclke
2 clk
5 globals
2 sr/we
1 cen/wclke
2 clk
realize_constants...
realized 1
place...
initial wire length = 1420
at iteration #50: temp = 13.704, wire length = 778
at iteration #100: temp = 8.20507, wire length = 562
at iteration #150: temp = 3.43071, wire length = 261
at iteration #200: temp = 0.951643, wire length = 195
final wire length = 158
After placement:
PIOs 8 / 206
PLBs 21 / 960
BRAMs 0 / 32
place time 0.12s
route...
gmake: *** [Makefile:11: example.asc] Illegal instruction (core dumped)
rm example.blif
gmake: Leaving directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx8k/work/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb'
*** Error code 2
Stop.
make: stopped in /usr/ports/devel/lattice-ice40-examples-hx8k