[package - main-i386-default][devel/lattice-ice40-examples-hx1k] Failed for lattice-ice40-examples-hx1k-g20180310_2 in build

From: <pkg-fallout_at_FreeBSD.org>
Date: Sat, 13 Apr 2024 11:01:57 UTC
You are receiving this mail as a port that you maintain
is failing to build on the FreeBSD package build server.
Please investigate the failure and submit a PR to fix
build.

Maintainer:     manu@FreeBSD.org
Log URL:        https://pkg-status.freebsd.org/beefy17/data/main-i386-default/pd866b4f57293_s4d7174b1d91/logs/lattice-ice40-examples-hx1k-g20180310_2.log
Build URL:      https://pkg-status.freebsd.org/beefy17/build.html?mastername=main-i386-default&build=pd866b4f57293_s4d7174b1d91
Log:

=>> Building devel/lattice-ice40-examples-hx1k
build started at Sat Apr 13 11:01:28 UTC 2024
port directory: /usr/ports/devel/lattice-ice40-examples-hx1k
package name: lattice-ice40-examples-hx1k-g20180310_2
building for: FreeBSD main-i386-default-job-13 15.0-CURRENT FreeBSD 15.0-CURRENT 1500018 i386
maintained by: manu@FreeBSD.org
Makefile datestamp: -rw-r--r--  1 root wheel 1433 Apr 25  2023 /usr/ports/devel/lattice-ice40-examples-hx1k/Makefile
Ports top last git commit: d866b4f5729
Ports top unclean checkout: no
Port dir last git commit: 8d3e020ed03
Port dir unclean checkout: no
Poudriere version: poudriere-git-3.4.1-1-g1e9f97d6
Host OSVERSION: 1500006
Jail OSVERSION: 1500018
Job Id: 13




!!! Jail is newer than host. (Jail: 1500018, Host: 1500006) !!!
!!! This is not supported. !!!
!!! Host kernel must be same or newer than jail. !!!
!!! Expect build failures. !!!



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=======================<phase: check-sanity   >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===>  License APACHE20 accepted by the user
===========================================================================
=======================<phase: pkg-depends    >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===>   lattice-ice40-examples-hx1k-g20180310_2 depends on file: /usr/local/sbin/pkg - not found
===>   Installing existing package /packages/All/pkg-1.21.1.pkg
[main-i386-default-job-13] Installing pkg-1.21.1...
[main-i386-default-job-13] Extracting pkg-1.21.1: .......... done
===>   lattice-ice40-examples-hx1k-g20180310_2 depends on file: /usr/local/sbin/pkg - found
===>   Returning to build of lattice-ice40-examples-hx1k-g20180310_2
===========================================================================
=======================<phase: fetch-depends  >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===========================================================================
=======================<phase: fetch          >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===>  License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_2 for building
===========================================================================
=======================<phase: checksum       >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===>  License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_2 for building
=> SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz.
===========================================================================
=======================<phase: extract-depends>============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===========================================================================
=======================<phase: extract        >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===>  License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_2 for building
===>  Extracting for lattice-ice40-examples-hx1k-g20180310_2
=> SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz.
===========================================================================
=======================<phase: patch-depends  >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===========================================================================
=======================<phase: patch          >============================
===== env: NO_DEPENDS=yes USER=root UID=0 GID=0
===>  Patching for lattice-ice40-examples-hx1k-g20180310_2
===========================================================================
=======================<phase: build-depends  >============================
===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0
===>   lattice-ice40-examples-hx1k-g20180310_2 depends on executable: abc - not found
===>   Installing existing package /packages/All/abc-g20220920.pkg
[main-i386-default-job-13] Installing abc-g20220920...
[main-i386-default-job-13] `-- Installing readline-8.2.10...
[main-i386-default-job-13] |   `-- Installing indexinfo-0.3.1...
[main-i386-default-job-13] |   `-- Extracting indexinfo-0.3.1: .... done
[main-i386-default-job-13] `-- Extracting readline-8.2.10: .......... done
[main-i386-default-job-13] Extracting abc-g20220920: ..... done
===>   lattice-ice40-examples-hx1k-g20180310_2 depends on executable: abc - found
===>   Returning to build of lattice-ice40-examples-hx1k-g20180310_2
===>   lattice-ice40-examples-hx1k-g20180310_2 depends on executable: arachne-pnr - not found
===>   Installing existing package /packages/All/arachne-pnr-g20181021_3.pkg
<snip>

2.43. Executing ICE40_WRAPCARRY pass (wrap carries).

2.44. Executing TECHMAP pass (map to technology primitives).

2.44.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.44.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 19 unused cells and 727 unused wires.

2.45. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:       60
  1-LUT                6
  2-LUT                9
  3-LUT               42
  4-LUT                3
  with \SB_CARRY    (#0)   36
  with \SB_CARRY    (#1)   36

Eliminating LUTs.
Number of LUTs:       60
  1-LUT                6
  2-LUT                9
  3-LUT               42
  4-LUT                3
  with \SB_CARRY    (#0)   36
  with \SB_CARRY    (#1)   36

Combining LUTs.
Number of LUTs:       59
  1-LUT                6
  2-LUT                8
  3-LUT               42
  4-LUT                3
  with \SB_CARRY    (#0)   36
  with \SB_CARRY    (#1)   36

Eliminated 0 LUTs.
Combined 1 LUTs.
<suppressed ~268 debug messages>

2.46. Executing TECHMAP pass (map to technology primitives).

2.46.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.46.2. Continuing TECHMAP pass.
Using template $paramod$d151c38cd9b2f723ca2e7bae80e30ea6d32d7878\$lut for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
No more expansions possible.
<suppressed ~257 debug messages>
Removed 0 unused cells and 123 unused wires.

2.47. Executing AUTONAME pass.
Renamed 973 objects in module top (38 iterations).
<suppressed ~260 debug messages>

2.48. Executing HIERARCHY pass (managing design hierarchy).

2.48.1. Analyzing design hierarchy..
Top module:  \top

2.48.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.49. Printing statistics.

=== top ===

   Number of wires:                119
   Number of wire bits:            170
   Number of public wires:         119
   Number of public wire bits:     170
   Number of ports:                  5
   Number of port bits:              5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                157
     SB_CARRY                       49
     SB_DFF                         16
     SB_DFFE                         1
     SB_DFFESR                      15
     SB_DFFESS                       1
     SB_DFFSR                       16
     SB_LUT4                        59

2.50. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

2.51. Executing BLIF backend.

End of script. Logfile hash: c1ddc7e605, CPU: user 5.98s system 0.02s, MEM: 31.91 MB peak
Yosys 0.40 (git sha1 a1bb0255d65, c++ 18.1.3 -O2 -fno-strict-aliasing -fPIC -Os)
Time spent: 68% 21x read_verilog (4 sec), 6% 27x opt_expr (0 sec), ...
arachne-pnr -d 1k -o example.asc -p ice40hx1k-evb.pcf example.blif -P vq100
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif example.blif...
prune...
read_pcf ice40hx1k-evb.pcf...
instantiate_io...
pack...

After packing:
IOs          5 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          85 / 1280
  DFF        16
  CARRY      20
  CARRY, DFF 33
  DFF PASS   4
  CARRY PASS 6
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 0

place_constraints...
promote_globals...
  promoted clk_24KHz, 38 / 38
  promoted LED1_m1_r_SB_DFFESS_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O, 17 / 17
  promoted BUT2_r_SB_LUT4_I2_O[1], 16 / 17
  promoted reset_SB_LUT4_I2_1_O, 14 / 14
  promoted CLK$2, 12 / 12
  promoted 5 nets
    2 sr/we
    1 cen/wclke
    2 clk
  5 globals
    2 sr/we
    1 cen/wclke
    2 clk
realize_constants...
  realized 1
place...
  initial wire length = 491
  at iteration #50: temp = 4.9361, wire length = 358
  at iteration #100: temp = 2.53391, wire length = 228
  at iteration #150: temp = 0.611955, wire length = 124
  final wire length = 99

After placement:
PIOs       8 / 72
PLBs       20 / 160
BRAMs      0 / 16

  place time 0.22s
route...
gmake: *** [Makefile:11: example.asc] Illegal instruction (core dumped)
rm example.blif
gmake: Leaving directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb'
*** Error code 2

Stop.
make: stopped in /usr/ports/devel/lattice-ice40-examples-hx1k