[package - main-i386-default][devel/lattice-ice40-examples-hx1k] Failed for lattice-ice40-examples-hx1k-g20180310_1 in build
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Date: Wed, 21 Sep 2022 02:57:23 UTC
You are receiving this mail as a port that you maintain
is failing to build on the FreeBSD package build server.
Please investigate the failure and submit a PR to fix
build.
Maintainer: manu@FreeBSD.org
Log URL: http://beefy17.nyi.freebsd.org/data/main-i386-default/p47ff75a1891e_s2c2ef670a7/logs/lattice-ice40-examples-hx1k-g20180310_1.log
Build URL: http://beefy17.nyi.freebsd.org/build.html?mastername=main-i386-default&build=p47ff75a1891e_s2c2ef670a7
Log:
=>> Building devel/lattice-ice40-examples-hx1k
build started at Wed Sep 21 02:57:02 UTC 2022
port directory: /usr/ports/devel/lattice-ice40-examples-hx1k
package name: lattice-ice40-examples-hx1k-g20180310_1
building for: FreeBSD main-i386-default-job-05 14.0-CURRENT FreeBSD 14.0-CURRENT 1400068 i386
maintained by: manu@FreeBSD.org
Makefile ident:
Poudriere version: 3.2.8-21-g883afb07
Host OSVERSION: 1400063
Jail OSVERSION: 1400068
Job Id: 05
!!! Jail is newer than host. (Jail: 1400068, Host: 1400063) !!!
!!! This is not supported. !!!
!!! Host kernel must be same or newer than jail. !!!
!!! Expect build failures. !!!
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=======================<phase: check-sanity >============================
===> License APACHE20 accepted by the user
===========================================================================
=======================<phase: pkg-depends >============================
===> lattice-ice40-examples-hx1k-g20180310_1 depends on file: /usr/local/sbin/pkg - not found
===> Installing existing package /packages/All/pkg-1.18.4.pkg
[main-i386-default-job-05] Installing pkg-1.18.4...
[main-i386-default-job-05] Extracting pkg-1.18.4: .......... done
===> lattice-ice40-examples-hx1k-g20180310_1 depends on file: /usr/local/sbin/pkg - found
===> Returning to build of lattice-ice40-examples-hx1k-g20180310_1
===========================================================================
=======================<phase: fetch-depends >============================
===========================================================================
=======================<phase: fetch >============================
===> License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_1 for building
===========================================================================
=======================<phase: checksum >============================
===> License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_1 for building
=> SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz.
===========================================================================
=======================<phase: extract-depends>============================
===========================================================================
=======================<phase: extract >============================
===> License APACHE20 accepted by the user
===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_1 for building
===> Extracting for lattice-ice40-examples-hx1k-g20180310_1
=> SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz.
===========================================================================
=======================<phase: patch-depends >============================
===========================================================================
=======================<phase: patch >============================
===> Patching for lattice-ice40-examples-hx1k-g20180310_1
===========================================================================
=======================<phase: build-depends >============================
===> lattice-ice40-examples-hx1k-g20180310_1 depends on executable: abc - not found
<snip>
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
2.32.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
2.32.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod$091610cd349a68bd5539cffd7126f0d76e9bca00\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~176 debug messages>
2.33. Executing OPT pass (performing simple optimizations).
2.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~143 debug messages>
2.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~54 debug messages>
Removed a total of 18 cells.
2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 46 unused cells and 76 unused wires.
<suppressed ~47 debug messages>
2.33.5. Finished fast OPT passes.
2.34. Executing ICE40_OPT pass (performing simple optimizations).
2.34.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$504.slice[0].carry: CO=\cntr [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$515.slice[0].carry: CO=\clk_div [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$518.slice[0].carry: CO=\cntr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$521.slice[0].carry: CO=\rst_cnt [0]
2.34.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.34.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 0 unused wires.
<suppressed ~1 debug messages>
2.34.6. Rerunning OPT passes. (Removed registers in this run.)
2.34.7. Running ICE40 specific optimizations.
2.34.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.34.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.34.12. Finished OPT passes. (There is nothing left to do.)
2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
2.36. Executing TECHMAP pass (map to technology primitives).
2.36.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.
2.36.2. Continuing TECHMAP pass.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_.
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
No more expansions possible.
<suppressed ~71 debug messages>
2.37. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>
2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$515.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$518.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$521.slice[0].carry ($lut).
2.39. Executing ICE40_OPT pass (performing simple optimizations).
2.39.1. Running ICE40 specific optimizations.
2.39.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~43 debug messages>
2.39.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~138 debug messages>
Removed a total of 46 cells.
2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 303 unused wires.
<suppressed ~1 debug messages>
2.39.6. Rerunning OPT passes. (Removed registers in this run.)
2.39.7. Running ICE40 specific optimizations.
2.39.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.39.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.39.12. Finished OPT passes. (There is nothing left to do.)
2.40. Executing TECHMAP pass (map to technology primitives).
2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
2.40.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
2.41. Executing ABC pass (technology mapping using ABC).
2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 56 gates and 83 wires to a netlist network with 27 inputs and 13 outputs.
2.41.1.1. Executing ABC.
ERROR: Can't open ABC output file `/tmp/yosys-abc-9cL2VH/output.blif'.
gmake[1]: *** [Makefile:8: example.blif] Error 1
gmake[1]: Leaving directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb'
*** Error code 2
Stop.
make: stopped in /usr/ports/devel/lattice-ice40-examples-hx1k