Re: watchdog timer programming
- Reply: mike tancsa : "Re: watchdog timer programming"
- In reply to: mike tancsa : "watchdog timer programming"
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Date: Tue, 24 Sep 2024 06:46:56 UTC
mike tancsa <mike@sentex.net> writes: > I am trying to get > > superio0: <ITE IT8613 SuperIO (revision 0x0c)> at port 0x2e-0x2f > on isa0 > itwd0: <Watchdog Timer on ITE SuperIO> at WDT ldn 0x07 on > superio0 > itwd0: Configured for system reset on timeout > > working on FreeBSD. The driver seems to load / attach fine, but > it does > not want to reboot the box. Adding a #define DIAGNOSTICS 1 > > shows > > itwd0: <Watchdog Timer on ITE SuperIO> at WDT ldn 0x07 on > superio0 > itwd0: Configured for system reset on timeout > itwd0: setting timeout to 4 > itwd0: setting timeout to 4 > itwd0: setting timeout to 4 > itwd0: setting timeout to 4 > itwd0: setting timeout to 4 > itwd0: setting timeout to 4 > > when I do > > watchdogd -t 3 > killall -9 watchdogd > > but never a reboot :( > > Any idea how to get this hardware working ? Do you know if, at least, the pre-timeout is working? Glancing at the code, this chip can be configured to use a specific IRQ (its default one is 0x40) and have an "NMI mode" (relying on an explicitly configured IRQ). Maybe playing with the dev.itwd.irq and .nwi tunables could get us some hints. Also this code from itwd's wd_func puzzle me a bit: superio_write(dev, 0x73, val); if (superio_read(dev, 0x73) != val) superio_write(dev, 0x73, val); It let me think that we either are writing twice to the same I/O port by mistake or the corresponding chip's register enforce a specific protocol to modify it. If the later, the code don't seems to be able to detect a "protocol error". By the way, do you have the datasheet of the ITE chip? (I know I must be very optimistic to ask such a question ;)) Regards, -- Stéphane Rochoy O: Stormshield