[Bug 270089] mpr: panic in mpr_complete_command during zpool import

https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=270089

--- Comment #21 from Dan Kotowski <dan.kotowski@a9development.com> ---
An interesting update from Solidrun:

https://developer.arm.com/documentation/ddi0517/f/functional-description/constraints-and-limitations-of-use/axi3-and-axi4-support

> The MMU-500 supports the AXI3 and AXI4 protocols when the sysbardisable_<tbuname> input signal is tied HIGH. In such cases, the following AXI3 features are not supported:
> 
> Write data interleaving
> 
> Write data and write address ordering must be the same, otherwise data corruption can occur.

NXP pulls this high in their PBI code. Could write-interleaving enablement be a
sysctl?

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