[Bug 269792] 13.2-BETA2: sigILL: lzma does not compile to westmere

https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=269792

--- Comment #5 from Peter Much <pmc@citylink.dinoex.sub.org> ---
Now this looks more interesting (I don't do that every day)

* thread #1, name = 'xz', stop reason = signal SIGILL
  * frame #0: 0x0000042592c15114 liblzma.so.5`lzma_crc64 + 276
    frame #1: 0x0000042592c14d67 liblzma.so.5`lzma_check_update + 87
    frame #2: 0x0000042592c09c70 liblzma.so.5`___lldb_unnamed_symbol389 + 256
    frame #3: 0x0000042592c0c6d4 liblzma.so.5`___lldb_unnamed_symbol407 + 484
    frame #4: 0x0000042592c050d8 liblzma.so.5`lzma_code + 424
    frame #5: 0x0000041d7187a3be xz`___lldb_unnamed_symbol238 + 1534
    frame #6: 0x0000041d7187e73c xz`___lldb_unnamed_symbol272 + 828
    frame #7: 0x0000041d71878602 xz

    0x42592c150f7 <+247>: shlq   $0x4, %rsi
    0x42592c150fb <+251>: xorl   %eax, %eax
    0x42592c150fd <+253>: movq   %r8, %xmm0
    0x42592c15102 <+258>: movdqa -0x199ba(%rip), %xmm4
    0x42592c1510a <+266>: nopw   (%rax,%rax)
    0x42592c15110 <+272>: movdqa %xmm1, %xmm5
->  0x42592c15114 <+276>: pclmulqdq $0x0, %xmm0, %xmm5
    0x42592c1511a <+282>: pxor   %xmm3, %xmm5
    0x42592c1511e <+286>: pclmulqdq $0x11, %xmm4, %xmm1
    0x42592c15124 <+292>: pxor   %xmm5, %xmm1
    0x42592c15128 <+296>: movdqa 0x10(%rdi), %xmm3
    0x42592c1512d <+301>: addq   $0x10, %rdi

Googling... hmm...
https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/carry-less-multiplication-instruction-in-gcm-mode-paper.pdf
"The Intel® PCLMULQDQ instruction is a new instruction available
beginning with the all new 2010 Intel® Core™ processor family
based on the 32nm Intel® microarchitecture codename Westmere."

CPU: Intel(R) Core(TM) i3 CPU         540  @ 3.07GHz (3059.12-MHz K8-class CPU)
  Origin="GenuineIntel"  Id=0x20655  Family=0x6  Model=0x25  Stepping=5
Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
Features2=0x9ae3bd<SSE3,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,POPCNT>
  AMD Features=0x28100800<SYSCALL,NX,RDTSCP,LM>
  AMD Features2=0x1<LAHF>
  Structured Extended Features3=0xc000000<IBPB,STIBP>
  VT-x: PAT,HLT,MTF,PAUSE,EPT,UG,VPID
  TSC: P-state invariant, performance statistics

 Launch Date Q1'10
 Intel® AES New Instructions No

Hm. So AES is only present in i7 series, not in Clarkdale and only part of
Arrandale.
I knew the chip doesn't support AES, but didn't know that they mixed it up so
horribly...

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