[Bug 265974] SMR has several missing barriers

https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=265974

--- Comment #5 from Mark Johnston <markj@FreeBSD.org> ---
(In reply to Konstantin Belousov from comment #3)
> That said, atomic_add_acq on x86 has the sequentially consistent semantic
already (which is why you said that it works on Intel, right?).  So the
#ifdef from the patch in smr_enter() is not needed, use seq_cst fence
for all arches.

The ifdef makes some sense as an optimization.  On x86 we can combine the store
and barrier into one instruction, so why not do that?

-- 
You are receiving this mail because:
You are the assignee for the bug.