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Hermes SMTP Server) with ESMTPA ID 81bf1afc4ef79cbe73bbd593926d9bea; Tue, 16 Jan 2024 00:30:26 +0000 (UTC) From: Mark Millard Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable List-Id: Porting FreeBSD to ARM processors List-Archive: https://lists.freebsd.org/archives/freebsd-arm List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-arm@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.300.61.1.2\)) Subject: History: The last armv7/AArch32 EL0..EL3 capable Cortex-A??'s ? Message-Id: <61E718D9-FDE1-4CD2-B699-101ED366706F@yahoo.com> Date: Mon, 15 Jan 2024 16:30:15 -0800 To: FreeBSD ARM List X-Mailer: Apple Mail (2.3774.300.61.1.2) References: <61E718D9-FDE1-4CD2-B699-101ED366706F.ref@yahoo.com> X-Spamd-Bar: -- X-Spamd-Result: default: False [-2.50 / 15.00]; NEURAL_HAM_LONG(-1.00)[-1.000]; SUBJECT_ENDS_QUESTION(1.00)[]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; MV_CASE(0.50)[]; DMARC_POLICY_ALLOW(-0.50)[yahoo.com,reject]; R_SPF_ALLOW(-0.20)[+ptr:yahoo.com]; R_DKIM_ALLOW(-0.20)[yahoo.com:s=s2048]; MIME_GOOD(-0.10)[text/plain]; RCVD_TLS_LAST(0.00)[]; TO_DN_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_ONE(0.00)[1]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; DWL_DNSWL_NONE(0.00)[yahoo.com:dkim]; FREEMAIL_FROM(0.00)[yahoo.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ASN(0.00)[asn:36647, ipnet:98.137.64.0/20, country:US]; FREEMAIL_ENVFROM(0.00)[yahoo.com]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; DKIM_TRACE(0.00)[yahoo.com:+]; MLMMJ_DEST(0.00)[freebsd-arm@freebsd.org]; RWL_MAILSPIKE_POSSIBLE(0.00)[98.137.69.206:from]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[98.137.69.206:from] X-Rspamd-Queue-Id: 4TDVKL1Zjwz4LlF In a multi-list discussion a reference was made to the last armv7 designs being from 2014. I had a vague recollection that the date did not span all the AArch32 EL0..EL3 capable hardware (that are also AArch64 capable) So I went looking . . . (Not that such detail changes the point made by much.) It appears that the last released AArch32 EL0..EL3 capable Cortex-A??'s are probably: Cortex-A55 r0p0 2016-Sept-30, r1p0 (public release) 2017-June-23, r2p0 = 2018-Nov-30 Cortex-A75 r0p0 2016-Sept-30, r2p0 (public release) 2017-June-03, r3p1 = 2018-Jul-27 (I've used the first Document History date for each r?p? above but have only listed the first Confidential, the first Non-Confidential, and the most recent r?p? dates.) More, later Cortex-A??/A??? hardware supports just EL0 for AArch32. But such is not able to boot AArch32 directly. (There appear to be some X-Gene EL0..EL2 AArch32 capable hardware and a EL0..EL3 as well. But I basically limited myself to the easier to check Cortex-A* family, depending on other's analysis that I'm familiar, with a little looking at ARM documents as well.) =3D=3D=3D Mark Millard marklmi at yahoo.com