From nobody Thu Feb 02 16:11:10 2023 X-Original-To: freebsd-arm@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4P73gQ30tGz3fns4 for ; Thu, 2 Feb 2023 16:11:14 +0000 (UTC) (envelope-from cracauer@cons.org) Received: from koef.zs64.net (koef.zs64.net [IPv6:2a00:14b0:4200:32e0::1e6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4P73gP6nhhz3hyP; Thu, 2 Feb 2023 16:11:13 +0000 (UTC) (envelope-from cracauer@cons.org) Authentication-Results: mx1.freebsd.org; none Received: from koef.zs64.net (koef.zs64.net [212.12.50.230]) by 0ons.org (8.16.1/8.15.2) with ESMTP id 312GBARi008800; Thu, 2 Feb 2023 16:11:10 GMT (envelope-from cracauer@koef.zs64.net) Received: (from cracauer@localhost) by koef.zs64.net (8.16.1/8.15.2/Submit) id 312GBAAm008799; Thu, 2 Feb 2023 11:11:10 -0500 (EST) (envelope-from cracauer) Date: Thu, 2 Feb 2023 11:11:10 -0500 From: Martin Cracauer To: John F Carr Cc: Martin Cracauer , "freebsd-arm@freebsd.org" , Andrew Turner Subject: Re: My ARM64 boot just broke (undefined instruction) Message-ID: References: <18399B6C-7F74-49B2-B21A-513FA5120589@mit.edu> List-Id: Porting FreeBSD to ARM processors List-Archive: https://lists.freebsd.org/archives/freebsd-arm List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-arm@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <18399B6C-7F74-49B2-B21A-513FA5120589@mit.edu> X-Rspamd-Queue-Id: 4P73gP6nhhz3hyP X-Spamd-Bar: ---- X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:13135, ipnet:2a00:14b0::/32, country:DE] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-ThisMailContainsUnwantedMimeParts: N John F Carr wrote on Thu, Feb 02, 2023 at 03:57:07PM +0000: > > On Feb 2, 2023, at 05:13, Martin Cracauer wrote: > > > > I am getting a new boot panic on 14-current. > > > > Platform: > > - Apple Mac M1 mini > > - QEMU 7.2.0 to arm64 > > - Last working kernel: Jan 25 main-n260242-f5924ad8fde4 > > - kern config GENERIC-NODEBUG > > > > [...] > > generic_timer0: irq 34,35,36 on acpi0 > > Undefined instruction: d53be228 > > That opcode disassembles to > mrs x8, CNTP_CTL_EL0 > The instruction is in function get_ctrl in sys/arm/arm/generic_timer.c. > > Three possibilities: > > 1. Apple didn't implement the CNTP_CTL_EL0 register to spec. > 2. qemu does not handle privileged access properly. > 3. There is something non-obvious wrong with the change below. Copying its author Andrew Turner. You could try reverting it. Thank you, John. I have confirmed that reverting the diff below solves the problem for me. Martin > commit c57694ce94712ce1fe0341ae51d70446a7dbbfa2 > Author: Andrew Turner > Date: Sat Jan 28 17:36:24 2023 +0000 > > Disable the arm physical timer when an irq exists > Some firmware leaves the timers enabled. Ensure they are disabled if > there are any physical timer interrupt resources to ensure we don't > receive any unexpected interrupts from them. > > diff --git a/sys/arm/arm/generic_timer.c b/sys/arm/arm/generic_timer.c > index 2527af9b9068..0556643032c2 100644 > --- a/sys/arm/arm/generic_timer.c > +++ b/sys/arm/arm/generic_timer.c > @@ -521,7 +521,8 @@ arm_tmr_attach(device_t dev) > if (sc->res[GT_VIRT] != NULL) > arm_tmr_disable(false); > /* And the physical */ > - if (sc->physical) > + if (sc->res[GT_PHYS_SECURE] != NULL || > + sc->res[GT_PHYS_NONSECURE] != NULL) > arm_tmr_disable(true); > -- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Martin Cracauer http://www.cons.org/cracauer/