From nobody Tue Nov 26 19:48:33 2024 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4XyY6B0dNHz5dvcw; Tue, 26 Nov 2024 19:48:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4XyY6B05fwz40pY; Tue, 26 Nov 2024 19:48:34 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1732650514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=xcSQp7wpcFu0qc9PfLYp6SLEttjUx11bzW9BqcICf8w=; b=K/SF8U45UYi7pnXntZMz6ZTXREzyv/s4x6MAIYYdOaGl6+pwAd8c0anDtW0OYxSDAR2vd/ iXtHQoqxLmF9XQTnidBcWkrKR3zSH4toRsEq6Ro6rHwiS7LcixQgJ4FfQBK48LYVVo9SjU wLtDtwUaWTtnQqZvK+A8mp64g2Zb5t0Mc0BAyTppOr0ekBcgEAQC03Cfj2epMd9Uq6h7hj 6wtiUrZhjaXyCyTZdYR9VByHVU6c2v7QS8lAP3zOEDHpn9AxlrGDR85PpOyG5HsWgDZ5oe bAM5Ky55KgxPef/5XVut2C807BMDi8gHIc48shSJhiqdH5DV01Hvh3Zfk+Vx5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1732650514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=xcSQp7wpcFu0qc9PfLYp6SLEttjUx11bzW9BqcICf8w=; b=xDxTCnVi8gboxFjSWucF3bJ9+z2GoN+EyU4i5V0vGox/jaeDEk4RZzeO4CJbIAxsNc8AJu 9rBO8keQ3rU5I7ZQUIRRuIQw2kUhbJc5MxF3rhychJgv5VCboshG2DyD5gBYWEBUYY0xHo yIsvpCcn7Pl3DZFgq8p3DnM+ZgYiosCGj9rgkXhLfzU2cvyUbblIwoAJXDBo0VhjvlKqlm nYPzzjUmdY6MGaQaJ/+jtaoXWHCyBgzC5Z/+VuLq2qLsfJ2R6NgDr6eKJgB58ADgTJpaQl o63N1c1NflBYy62JGEZ14EIwgAURIFm7SDfPsSQSZ72h+ZVTYcb8oMWewceSFg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1732650514; a=rsa-sha256; cv=none; b=PTKRmD0jeg/OVdkCaFKwrZC8A9gKWLol7o5IHv14leerAQYMgLCOaq7oYLtqsQZ0C9r+45 KiguG0PB5IOQBce/HgGfHP0sYdPyvLbC9mufd3RRG10d/+ZU77JBtEgfZhSRxXTqp36LRq U6t5rQbAvVgRukLs5p73INIYpyVyFL1b7SxsfC5B7wahU3PswGJQHH8LI6VqijyKbe2CFQ DG/Csyuie93t5PzR5/5226g3fcbijPpekvdBwCPLIO7okHLRFl3rhy2eYvWEtJYVopWKM5 luIBSq3JHpw4CgHqKYt7sG83sJhcO4BSBpLNOJkiDIArU0Gc9rfH3RuucCO72w== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4XyY696XgLzfHb; Tue, 26 Nov 2024 19:48:33 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 4AQJmXvx042169; Tue, 26 Nov 2024 19:48:33 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 4AQJmXJx042166; Tue, 26 Nov 2024 19:48:33 GMT (envelope-from git) Date: Tue, 26 Nov 2024 19:48:33 GMT Message-Id: <202411261948.4AQJmXJx042166@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Konstantin Belousov Subject: git: 28fdf718b30b - main - amd64: add machine/pte.h List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kib X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 28fdf718b30b43d1f9ecaa1d2de021d7b53f8a67 Auto-Submitted: auto-generated The branch main has been updated by kib: URL: https://cgit.FreeBSD.org/src/commit/?id=28fdf718b30b43d1f9ecaa1d2de021d7b53f8a67 commit 28fdf718b30b43d1f9ecaa1d2de021d7b53f8a67 Author: Konstantin Belousov AuthorDate: 2024-11-25 23:10:34 +0000 Commit: Konstantin Belousov CommitDate: 2024-11-26 19:48:27 +0000 amd64: add machine/pte.h Following arm64 and risc-v, move definitions that describe hardware-enforced layout of PTEs and #PF error bits, into a dedicated header. Reviewed by: markj Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D47749 --- sys/amd64/include/pmap.h | 58 +------------------------- sys/amd64/include/pte.h | 104 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 105 insertions(+), 57 deletions(-) diff --git a/sys/amd64/include/pmap.h b/sys/amd64/include/pmap.h index adeb89d08bb5..da32b3b087b7 100644 --- a/sys/amd64/include/pmap.h +++ b/sys/amd64/include/pmap.h @@ -47,48 +47,7 @@ #ifndef _MACHINE_PMAP_H_ #define _MACHINE_PMAP_H_ -/* - * Page-directory and page-table entries follow this format, with a few - * of the fields not present here and there, depending on a lot of things. - */ - /* ---- Intel Nomenclature ---- */ -#define X86_PG_V 0x001 /* P Valid */ -#define X86_PG_RW 0x002 /* R/W Read/Write */ -#define X86_PG_U 0x004 /* U/S User/Supervisor */ -#define X86_PG_NC_PWT 0x008 /* PWT Write through */ -#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ -#define X86_PG_A 0x020 /* A Accessed */ -#define X86_PG_M 0x040 /* D Dirty */ -#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ -#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ -#define X86_PG_G 0x100 /* G Global */ -#define X86_PG_AVAIL1 0x200 /* / Available for system */ -#define X86_PG_AVAIL2 0x400 /* < programmers use */ -#define X86_PG_AVAIL3 0x800 /* \ */ -#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ -#define X86_PG_PKU(idx) ((pt_entry_t)idx << 59) -#define X86_PG_NX (1ul<<63) /* No-execute */ -#define X86_PG_AVAIL(x) (1ul << (x)) - -/* Page level cache control fields used to determine the PAT type */ -#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) -#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) - -/* Protection keys indexes */ -#define PMAP_MAX_PKRU_IDX 0xf -#define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX) - -/* - * Intel extended page table (EPT) bit definitions. - */ -#define EPT_PG_READ 0x001 /* R Read */ -#define EPT_PG_WRITE 0x002 /* W Write */ -#define EPT_PG_EXECUTE 0x004 /* X Execute */ -#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ -#define EPT_PG_PS 0x080 /* PS Page size */ -#define EPT_PG_A 0x100 /* A Accessed */ -#define EPT_PG_M 0x200 /* D Dirty */ -#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */ +#include /* * Define the PG_xx macros in terms of the bits on x86 PTEs. @@ -117,9 +76,6 @@ #define EPT_PG_EMUL_V X86_PG_AVAIL(52) #define EPT_PG_EMUL_RW X86_PG_AVAIL(53) #define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */ -#define PG_FRAME (0x000ffffffffff000ul) -#define PG_PS_FRAME (0x000fffffffe00000ul) -#define PG_PS_PDP_FRAME (0x000fffffc0000000ul) /* * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB @@ -128,18 +84,6 @@ #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \ PG_M | PG_U | PG_RW | PG_V | PG_PKU_MASK) -/* - * Page Protection Exception bits - */ - -#define PGEX_P 0x01 /* Protection violation vs. not present */ -#define PGEX_W 0x02 /* during a Write cycle */ -#define PGEX_U 0x04 /* access from User mode (UPL) */ -#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ -#define PGEX_I 0x10 /* during an instruction fetch */ -#define PGEX_PK 0x20 /* protection key violation */ -#define PGEX_SGX 0x8000 /* SGX-related */ - /* * undef the PG_xx macros that define bits in the regular x86 PTEs that * have a different position in nested PTEs. This is done when compiling diff --git a/sys/amd64/include/pte.h b/sys/amd64/include/pte.h new file mode 100644 index 000000000000..5195bdc224f8 --- /dev/null +++ b/sys/amd64/include/pte.h @@ -0,0 +1,104 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2003 Peter Wemm. + * Copyright (c) 1991 Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and William Jolitz of UUNET Technologies Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Derived from hp300 version by Mike Hibler, this version by William + * Jolitz uses a recursive map [a pde points to the page directory] to + * map the page tables using the pagetables themselves. This is done to + * reduce the impact on kernel virtual memory for lots of sparse address + * space, and to reduce the cost of memory to each process. + */ + +#ifndef _MACHINE_PTE_H_ +#define _MACHINE_PTE_H_ + +/* + * Page-directory and page-table entries follow this format, with a few + * of the fields not present here and there, depending on a lot of things. + */ + /* ---- Intel Nomenclature ---- */ +#define X86_PG_V 0x001 /* P Valid */ +#define X86_PG_RW 0x002 /* R/W Read/Write */ +#define X86_PG_U 0x004 /* U/S User/Supervisor */ +#define X86_PG_NC_PWT 0x008 /* PWT Write through */ +#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ +#define X86_PG_A 0x020 /* A Accessed */ +#define X86_PG_M 0x040 /* D Dirty */ +#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ +#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ +#define X86_PG_G 0x100 /* G Global */ +#define X86_PG_AVAIL1 0x200 /* / Available for system */ +#define X86_PG_AVAIL2 0x400 /* < programmers use */ +#define X86_PG_AVAIL3 0x800 /* \ */ +#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ +#define X86_PG_PKU(idx) ((pt_entry_t)idx << 59) +#define X86_PG_NX (1ul<<63) /* No-execute */ +#define X86_PG_AVAIL(x) (1ul << (x)) + +/* Page level cache control fields used to determine the PAT type */ +#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) +#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) + +/* Protection keys indexes */ +#define PMAP_MAX_PKRU_IDX 0xf +#define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX) + +/* + * Intel extended page table (EPT) bit definitions. + */ +#define EPT_PG_READ 0x001 /* R Read */ +#define EPT_PG_WRITE 0x002 /* W Write */ +#define EPT_PG_EXECUTE 0x004 /* X Execute */ +#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ +#define EPT_PG_PS 0x080 /* PS Page size */ +#define EPT_PG_A 0x100 /* A Accessed */ +#define EPT_PG_M 0x200 /* D Dirty */ +#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */ + +#define PG_FRAME (0x000ffffffffff000ul) +#define PG_PS_FRAME (0x000fffffffe00000ul) +#define PG_PS_PDP_FRAME (0x000fffffc0000000ul) + +/* + * Page Protection Exception bits + */ +#define PGEX_P 0x01 /* Protection violation vs. not present */ +#define PGEX_W 0x02 /* during a Write cycle */ +#define PGEX_U 0x04 /* access from User mode (UPL) */ +#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ +#define PGEX_I 0x10 /* during an instruction fetch */ +#define PGEX_PK 0x20 /* protection key violation */ +#define PGEX_SGX 0x8000 /* SGX-related */ + +#endif