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Date: Wed, 22 May 2024 16:06:54 GMT
Message-Id: <202405221606.44MG6st5072565@gitrepo.freebsd.org>
To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org,
dev-commits-src-main@FreeBSD.org
From: Ruslan Bukin
Subject: git: 2183004e14a8 - main - riscv: Implement atomic operations
List-Id: Commit messages for the main branch of the src repository
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X-Git-Committer: br
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X-Git-Commit: 2183004e14a863d65ca9192df1bea2625e3fdfb3
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The branch main has been updated by br:
URL: https://cgit.FreeBSD.org/src/commit/?id=2183004e14a863d65ca9192df1bea2625e3fdfb3
commit 2183004e14a863d65ca9192df1bea2625e3fdfb3
Author: Ruslan Bukin
AuthorDate: 2024-05-22 15:07:27 +0000
Commit: Ruslan Bukin
CommitDate: 2024-05-22 15:45:11 +0000
riscv: Implement atomic operations
Implement atomic_load_acq_16, atomic_store_rel_16.
These are needed by bhyve(8) PCIe bus emulation code.
Group 16-bit atomic functions similarly to 32 and 64-bit.
Reviewed by: mhorne
Differential Revision: https://reviews.freebsd.org/D45228
---
sys/riscv/include/atomic.h | 37 ++++++++++++++++++++++++++++++++-----
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/sys/riscv/include/atomic.h b/sys/riscv/include/atomic.h
index ef9aa5ef057d..03c1327d74da 100644
--- a/sys/riscv/include/atomic.h
+++ b/sys/riscv/include/atomic.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2015 Ruslan Bukin
+ * Copyright (c) 2015-2024 Ruslan Bukin
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@@ -105,8 +105,6 @@ atomic_fcmpset_rel_##WIDTH(__volatile uint##WIDTH##_t *p, \
ATOMIC_CMPSET_ACQ_REL(8);
ATOMIC_FCMPSET_ACQ_REL(8);
-ATOMIC_CMPSET_ACQ_REL(16);
-ATOMIC_FCMPSET_ACQ_REL(16);
#define atomic_cmpset_char atomic_cmpset_8
#define atomic_cmpset_acq_char atomic_cmpset_acq_8
@@ -116,11 +114,40 @@ ATOMIC_FCMPSET_ACQ_REL(16);
#define atomic_fcmpset_rel_char atomic_fcmpset_rel_8
#define atomic_cmpset_short atomic_cmpset_16
-#define atomic_cmpset_acq_short atomic_cmpset_acq_16
-#define atomic_cmpset_rel_short atomic_cmpset_rel_16
#define atomic_fcmpset_short atomic_fcmpset_16
+
+ATOMIC_CMPSET_ACQ_REL(16);
+ATOMIC_FCMPSET_ACQ_REL(16);
+
+#define atomic_load_acq_16 atomic_load_acq_16
+static __inline uint16_t
+atomic_load_acq_16(volatile uint16_t *p)
+{
+ uint16_t ret;
+
+ ret = *p;
+
+ fence();
+
+ return (ret);
+}
+
+static __inline void
+atomic_store_rel_16(volatile uint16_t *p, uint16_t val)
+{
+
+ fence();
+
+ *p = val;
+}
+
+#define atomic_cmpset_acq_short atomic_cmpset_acq_16
#define atomic_fcmpset_acq_short atomic_fcmpset_acq_16
+#define atomic_load_acq_short atomic_load_acq_16
+
+#define atomic_cmpset_rel_short atomic_cmpset_rel_16
#define atomic_fcmpset_rel_short atomic_fcmpset_rel_16
+#define atomic_store_rel_short atomic_store_rel_16
static __inline void
atomic_add_32(volatile uint32_t *p, uint32_t val)