From nobody Mon Dec 16 19:27:57 2024 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4YBqj970l9z5fsdm; Mon, 16 Dec 2024 19:27:57 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4YBqj94zSVz4kVW; Mon, 16 Dec 2024 19:27:57 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1734377277; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=5cPqzuUcIM0TBNvEjIyHF/Uq1zIeglOWgJZiHHvDWYk=; b=p3/AYbUJEEJaB4iHpf5bFh4LwNHJhxjESJpZHai9lTJUCR8IFu9NIy+Wfs3c8lc7nbkcDB cxh/OilZEGaYVsEUSxxi9YOpB40SykT7XePdUcMG8ylUzgd9wA9VYl4iJQiyxrxrB3khve ZknGjthu9qYETg4tGj/a1Yrv71P1LkfxGSCBP79PMICf0dNqEy3cLcRqsEzLdtSF1ragFO t/yN4CEwxy3Dzxvvum8+45Xvix/heffoAi1gBVVs/G6azI0erJEVAuFUHqMXpIn9vXhwM6 mpkBFKORpmCQ6CP5eO0l1+fYtf5ndsQ6vyqyhj06cW5WbqPyeQYopr21w/suyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1734377277; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=5cPqzuUcIM0TBNvEjIyHF/Uq1zIeglOWgJZiHHvDWYk=; b=xko/L/S3GSXOEmWE04TdY7GjazhyO+hHkEQYMs8u68PNQD4HuFM9xUNjTO4kISF4FdAln4 YBJQw7ydFUWhLibE9xLFceTnnyVe8bk2lyiYOt7tsXIqTBpqcz6ZF3QHoX1oGQKwzTQynO FK2RLlQOOi8L8XjSum7bn57lT+MXXXadfg9P18jV8d5VQa8wM+7SCH5CNf5I74hkupdRSO NC6rciZXSeeoQVI2Ra97w1EuCDBeEEl9mjWBkCrK+/qBEfihBGyjFvTnrqXjG/uomqb6h2 8OSn4lrmZ+rIoioO5VmL1IGACAzwREgAFwHlNNX3sNdhfkO18xQT6/3VWG6zIQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1734377277; a=rsa-sha256; cv=none; b=ErGic/qd4J95hlOiRfCL63AQ9ELuEfYxCEBJl/j0NYKDP5kQgeU8hXJEf0DitC/YDYS75Q RKvZ4VIAe48mBh07rPoVUlyKRIEnvNaA/LAnwGOwGgS1/9CEKmqt2fE6pHp2OuLXaCSuHw IaJg9DLXGSL692uP91meYHab6vMWVrTMV5ZJqTquv7CJRhy2+EH76r4IKXXS3SCcXQ2A7z hx3tsB1hDFjBOhA/ZSNCluL4CZxddWDaVEKR4RQ2r9NjDi1giVpzW1t30BH8qkJxdXY+qe xEzBakK3lr5FbyiUihaeDbpJxWZP+rOlqtt8V2xyhSmkVjPetKy2adOjvqJipg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4YBqj946pxz169Z; Mon, 16 Dec 2024 19:27:57 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 4BGJRvoI078593; Mon, 16 Dec 2024 19:27:57 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 4BGJRvVD078590; Mon, 16 Dec 2024 19:27:57 GMT (envelope-from git) Date: Mon, 16 Dec 2024 19:27:57 GMT Message-Id: <202412161927.4BGJRvVD078590@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: 35a2229b6791 - main - Add StarFive JH7110's STG clocks List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 35a2229b67914ff1a4bae6334ad5015aa603967a Auto-Submitted: auto-generated The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=35a2229b67914ff1a4bae6334ad5015aa603967a commit 35a2229b67914ff1a4bae6334ad5015aa603967a Author: Jari Sihvola AuthorDate: 2024-12-16 19:26:12 +0000 Commit: Mitchell Horne CommitDate: 2024-12-16 19:27:23 +0000 Add StarFive JH7110's STG clocks This is identical to AON clocks. The only difference is BUS_PASS_ORDER_LAST which was needed for some reason. This has clocks needed by PCIe controller driver. Reviewed by: mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D47920 --- sys/dev/clk/starfive/jh7110_clk_stg.c | 204 ++++++++++++++++++++++++++++++++++ sys/riscv/starfive/files.starfive | 1 + 2 files changed, 205 insertions(+) diff --git a/sys/dev/clk/starfive/jh7110_clk_stg.c b/sys/dev/clk/starfive/jh7110_clk_stg.c new file mode 100644 index 000000000000..af30e640ecf6 --- /dev/null +++ b/sys/dev/clk/starfive/jh7110_clk_stg.c @@ -0,0 +1,204 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 Jari Sihvola + */ + +/* Clocks for STG group. PLL_OUT & SYS clocks must be registered first. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "clkdev_if.h" +#include "hwreset_if.h" + +static struct ofw_compat_data compat_data[] = { + { "starfive,jh7110-stgcrg", 1 }, + { NULL, 0 } +}; + +static struct resource_spec res_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + RESOURCE_SPEC_END +}; + +/* parents */ +static const char *e2_rtc_p[] = { "osc" }; +static const char *e2_core_p[] = { "stg_axiahb" }; +static const char *e2_dbg_p[] = { "stg_axiahb" }; + +static const char *pcie_slv_main_p[] = { "stg_axiahb" }; +static const char *pcie0_tl_p[] = { "stg_axiahb" }; +static const char *pcie1_tl_p[] = { "stg_axiahb" }; +static const char *pcie0_axi_mst0_p[] = { "stg_axiahb" }; +static const char *pcie1_axi_mst0_p[] = { "stg_axiahb" }; +static const char *pcie0_apb_p[] = { "apb_bus" }; +static const char *pcie1_apb_p[] = { "apb_bus" }; + +static const char *usb0_lpm_p[] = { "osc" }; +static const char *usb0_stb_p[] = { "osc" }; +static const char *usb0_apb_p[] = { "apb_bus" }; +static const char *usb0_utmi_apb_p[] = { "apb_bus" }; +static const char *usb0_axi_p[] = { "stg_axiahb" }; +static const char *usb0_app_125_p[] = { "usb_125m" }; +static const char *usb0_refclk_p[] = { "osc" }; + +static const char *dma1p_axi_p[] = { "stg_axiahb" }; +static const char *dma1p_ahb_p[] = { "stg_axiahb" }; + +/* STG clocks */ +static const struct jh7110_clk_def stg_clks[] = { + JH7110_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", usb0_apb_p), + JH7110_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", + usb0_utmi_apb_p), + JH7110_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", usb0_axi_p), + JH7110_GATEDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", usb0_lpm_p, 2), + JH7110_GATEDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", usb0_stb_p, 4), + JH7110_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", usb0_app_125_p), + JH7110_DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", usb0_refclk_p, 2), + + JH7110_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", + pcie0_axi_mst0_p), + JH7110_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", pcie0_apb_p), + JH7110_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", pcie0_tl_p), + JH7110_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", + pcie1_axi_mst0_p), + + JH7110_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", pcie1_apb_p), + JH7110_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", pcie1_tl_p), + JH7110_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", + pcie_slv_main_p), + + JH7110_GATEDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", e2_rtc_p, 24), + JH7110_GATE(JH7110_STGCLK_E2_CORE, "e2_core", e2_core_p), + JH7110_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", e2_dbg_p), + + JH7110_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", dma1p_axi_p), + JH7110_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", dma1p_ahb_p), +}; + +static int +jh7110_clk_stg_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "StarFive JH7110 STG clock generator"); + + return (BUS_PROBE_DEFAULT); +} + +static int +jh7110_clk_stg_attach(device_t dev) +{ + struct jh7110_clkgen_softc *sc; + int err; + + sc = device_get_softc(dev); + + sc->reset_status_offset = STGCRG_RESET_STATUS; + sc->reset_selector_offset = STGCRG_RESET_SELECTOR; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + err = bus_alloc_resources(dev, res_spec, &sc->mem_res); + if (err != 0) { + device_printf(dev, "Couldn't allocate resources, error %d\n", + err); + return (ENXIO); + } + + sc->clkdom = clkdom_create(dev); + if (sc->clkdom == NULL) { + device_printf(dev, "Couldn't create clkdom, error %d\n", err); + return (ENXIO); + } + + for (int i = 0; i < nitems(stg_clks); i++) { + err = jh7110_clk_register(sc->clkdom, &stg_clks[i]); + if (err != 0) { + device_printf(dev, + "Couldn't register clk %s, error %d\n", + stg_clks[i].clkdef.name, err); + return (ENXIO); + } + } + + if (clkdom_finit(sc->clkdom) != 0) + panic("Cannot finalize clkdom initialization\n"); + + if (bootverbose) + clkdom_dump(sc->clkdom); + + hwreset_register_ofw_provider(dev); + + return (0); +} + +static void +jh7110_clk_stg_device_lock(device_t dev) +{ + struct jh7110_clkgen_softc *sc; + + sc = device_get_softc(dev); + mtx_lock(&sc->mtx); +} + +static void +jh7110_clk_stg_device_unlock(device_t dev) +{ + struct jh7110_clkgen_softc *sc; + + sc = device_get_softc(dev); + mtx_unlock(&sc->mtx); +} + +static int +jh7110_clk_stg_detach(device_t dev) +{ + /* Detach not supported */ + return (EBUSY); +} + +static device_method_t jh7110_clk_stg_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, jh7110_clk_stg_probe), + DEVMETHOD(device_attach, jh7110_clk_stg_attach), + DEVMETHOD(device_detach, jh7110_clk_stg_detach), + + /* clkdev interface */ + DEVMETHOD(clkdev_device_lock, jh7110_clk_stg_device_lock), + DEVMETHOD(clkdev_device_unlock, jh7110_clk_stg_device_unlock), + + /* Reset interface */ + DEVMETHOD(hwreset_assert, jh7110_reset_assert), + DEVMETHOD(hwreset_is_asserted, jh7110_reset_is_asserted), + + DEVMETHOD_END +}; + +DEFINE_CLASS_0(jh7110_stg, jh7110_stg_driver, jh7110_clk_stg_methods, + sizeof(struct jh7110_clkgen_softc)); +EARLY_DRIVER_MODULE(jh7110_stg, simplebus, jh7110_stg_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_LATE + 1); +MODULE_VERSION(jh7110_stg, 1); diff --git a/sys/riscv/starfive/files.starfive b/sys/riscv/starfive/files.starfive index d867dee1099b..10c56448970d 100644 --- a/sys/riscv/starfive/files.starfive +++ b/sys/riscv/starfive/files.starfive @@ -2,6 +2,7 @@ dev/clk/starfive/jh7110_clk.c standard dev/clk/starfive/jh7110_clk_aon.c standard dev/clk/starfive/jh7110_clk_pll.c standard dev/clk/starfive/jh7110_clk_sys.c standard +dev/clk/starfive/jh7110_clk_stg.c standard dev/mmc/host/dwmmc_starfive.c optional dwmmc_starfive fdt riscv/starfive/starfive_syscon.c standard