git: ce3fbcdd14a1 - main - jh7110: Add sys clocks for STG & PCIE
- Go to: [ bottom of page ] [ top of archives ] [ this month ]
Date: Mon, 16 Dec 2024 19:27:56 UTC
The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=ce3fbcdd14a1a2ef90890fb8da9592fb4c349b35 commit ce3fbcdd14a1a2ef90890fb8da9592fb4c349b35 Author: Jari Sihvola <jsihv@gmx.com> AuthorDate: 2024-12-16 19:21:50 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2024-12-16 19:27:23 +0000 jh7110: Add sys clocks for STG & PCIE This patch adds some SYS clocks for StarFive JH7110. They are necessary for getting STG clocks and PCIe driver working. Reviewed by: mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D47981 --- sys/dev/clk/starfive/jh7110_clk_sys.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sys/dev/clk/starfive/jh7110_clk_sys.c b/sys/dev/clk/starfive/jh7110_clk_sys.c index e7b8aa87c48e..4bc29b20bc91 100644 --- a/sys/dev/clk/starfive/jh7110_clk_sys.c +++ b/sys/dev/clk/starfive/jh7110_clk_sys.c @@ -56,6 +56,8 @@ static const char *u0_sys_iomux_apb_p[] = { "apb_bus" }; static const char *stg_axiahb_p[] = { "axi_cfg0" }; static const char *ahb0_p[] = { "stg_axiahb" }; static const char *axi_cfg0_p[] = { "bus_root" }; +static const char *nocstg_bus_p[] = { "bus_root" }; +static const char *noc_bus_stg_axi_p[] = { "nocstg_bus" }; static const char *u0_dw_uart_clk_apb_p[] = { "apb0" }; static const char *u0_dw_uart_clk_core_p[] = { "osc" }; @@ -65,6 +67,7 @@ static const char *u1_dw_uart_clk_apb_p[] = { "apb0" }; static const char *u1_dw_uart_clk_core_p[] = { "osc" }; static const char *u1_dw_sdio_clk_ahb_p[] = { "ahb0" }; static const char *u1_dw_sdio_clk_sdcard_p[] = { "axi_cfg0" }; +static const char *usb_125m_p[] = { "pll0_out" }; static const char *u2_dw_uart_clk_apb_p[] = { "apb0" }; static const char *u2_dw_uart_clk_core_p[] = { "osc" }; static const char *u3_dw_uart_clk_apb_p[] = { "apb0" }; @@ -116,6 +119,9 @@ static const struct jh7110_clk_def sys_clks[] = { JH7110_DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", axi_cfg0_p, 3), JH7110_DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", stg_axiahb_p, 2), + JH7110_DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", nocstg_bus_p, 3), + JH7110_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", + noc_bus_stg_axi_p), JH7110_GATE(JH7110_SYSCLK_AHB0, "ahb0", ahb0_p), JH7110_DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", apb_bus_p, 8), @@ -127,6 +133,7 @@ static const struct jh7110_clk_def sys_clks[] = { u0_dw_sdio_clk_sdcard_p, 15), JH7110_GATEDIV(JH7110_SYSCLK_SDIO1_SDCARD, "u1_dw_sdio_clk_sdcard", u1_dw_sdio_clk_sdcard_p, 15), + JH7110_DIV(JH7110_SYSCLK_USB_125M, "usb_125m", usb_125m_p, 15), JH7110_DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", gmac_src_p, 7), JH7110_GATEDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk",