From nobody Sun Dec 15 15:40:38 2024 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4YB6jL5DsSz5gy60; Sun, 15 Dec 2024 15:40:38 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4YB6jL39Njz40Hn; Sun, 15 Dec 2024 15:40:38 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1734277238; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=0rZtaXTDkO6TJ/psRwpzdWGwzo/eU5GDAsVHZg/E2hc=; b=Y43Z3lNYkU4GAkG1un2TrCvfMKAr/G2+ikZVIFt7Bnn6o16voRSNpXh1WdoIbrBF2VzIhE lNBLoWWmTxa6ubAErb7f2pXlRSjX5yTe15R9PVtqvyHU3NEsRS9XPqrBHpNT+vtK6XmjN1 xrEnFdbNoS6sGxC7t72q50ft77p464kFOjBZCmC7FnAyDDnZ0Jp3teROAn1UCvSFXgPxaM 6Bz3Tkkv2MJBPzxbvRi03/vCy770F1dU+QNHyGIRHdtGkNuJcu5b8DEqciAeJc+MxCMWti eMiKtQNsHJN1om+ijGVt0JSxSmIaOvITb67Mo5WGfbhkOLLrlecNg35eZKAfnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1734277238; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=0rZtaXTDkO6TJ/psRwpzdWGwzo/eU5GDAsVHZg/E2hc=; b=dKV3jp5I/p+/SXcugZoJcIgbgnaaJaEyCv6mp9uq1e29A67bFEHqz0AJO+OIT/Gzz4ppmW 0u1nJMLI7nqcX10AekIQnxHa1PmftN1kSSjGfn/wsXHZjQWxSbRIlpXaeakoXzokKxFPcK M4ADxM3jeAqMTviIvbeufTroqkbAuLTVcNKw8hmmbWRiVrwJq9EwGOaoGxg5go9TdHa/vw YOY4xcid7ZzLEHVWLgUhVBacJQmRebSM4kbCjc/852QOAhOYoY+qqwb5diPgGUnBgTFWO6 DIkzitRg2xugvHG9ty4ktu2PYnIftxtcvSzDRpXeMW0MHsvLZWS7xyyc0vEXUw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1734277238; a=rsa-sha256; cv=none; b=V9So7Oi743toKVoCSSdt2Ma67hFUaMMQ2tjZgdtMYlBsMwMrFLrfAiCcf/VafqGT+VRJMd cdRwg/tIxBSozNakNgtQ9LDnzcWsrNwNU4BhOHHPmZYTu2PZwAsPL4Drbgnvr6U9x0X0Hr dE54/p75v+O+fO2s2/9iv+zjttBxFn58x3anCfJi6VmxrqvE9W8krkkRWMdbFG40hod8wU XdOMa/cLVcjGNqRiN5ReGB+UDY9po5Bv3N+NiGlwMq/ryPk6C8TNnu0Mrn1U2qO8URtsOk I+oIUxqG+t6HoQQraHLiph/inJfpvrHZp/Z6XcQrOVYYxWDse9eu54WgIWwKBQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4YB6jL2nd5z1Chw; Sun, 15 Dec 2024 15:40:38 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 4BFFec57069457; Sun, 15 Dec 2024 15:40:38 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 4BFFecLY069454; Sun, 15 Dec 2024 15:40:38 GMT (envelope-from git) Date: Sun, 15 Dec 2024 15:40:38 GMT Message-Id: <202412151540.4BFFecLY069454@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Bojan =?utf-8?Q?Novkovi=C4=87?= Subject: git: 0c4fa0bdcf87 - main - x86: Add definitions for some Intel Processor Trace bits List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: bnovkov X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 0c4fa0bdcf87bee66d749c7550da852717522bdf Auto-Submitted: auto-generated The branch main has been updated by bnovkov: URL: https://cgit.FreeBSD.org/src/commit/?id=0c4fa0bdcf87bee66d749c7550da852717522bdf commit 0c4fa0bdcf87bee66d749c7550da852717522bdf Author: Bojan Novković AuthorDate: 2024-12-15 14:03:34 +0000 Commit: Bojan Novković CommitDate: 2024-12-15 15:39:36 +0000 x86: Add definitions for some Intel Processor Trace bits This patch adds definitions for Intel PT-related MSRs and several PT feature bits. Reviewed by: kib, markj Differential Revision: https://reviews.freebsd.org/D46419 --- sys/x86/include/specialreg.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 9dc30e31e540..e9dde5c3b46a 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -123,6 +123,7 @@ #define XFEATURE_ENABLED_OPMASK 0x00000020 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 +#define XFEATURE_ENABLED_PT 0x00000100 #define XFEATURE_ENABLED_PKRU 0x00000200 #define XFEATURE_ENABLED_TILECONFIG 0x00020000 #define XFEATURE_ENABLED_TILEDATA 0x00040000 @@ -213,6 +214,7 @@ #define CPUPT_MTC (1 << 3) /* MTC Supported */ #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ +#define CPUPT_DIS_TNT (1 << 8) /* TNT disable supported */ /* Leaf 0 ecx. */ #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ @@ -654,6 +656,12 @@ #define MSR_PAT 0x277 #define MSR_MC0_CTL2 0x280 #define MSR_MTRRdefType 0x2ff +#define MSR_IA_GLOBAL_STATUS 0x38E +#define MSR_IA_GLOBAL_CTRL 0x38F +#define MSR_IA_GLOBAL_OVF_CTRL 0x390 +#define MSR_IA_GLOBAL_STATUS_RESET 0x390 +#define MSR_IA_GLOBAL_STATUS_SET 0x391 +#define GLOBAL_STATUS_FLAG_TRACETOPAPMI (1ULL << 55) #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 @@ -781,6 +789,7 @@ #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S) #define RTIT_CTL_ADDR3_CFG_S 44 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S) +#define RTIT_CTL_DIS_TNT (1ULL << 55) #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */ #define RTIT_STATUS_FILTEREN (1 << 0) #define RTIT_STATUS_CONTEXTEN (1 << 1)