git: 4056e774b1b3 - main - arm64: Move setting TCR_HD to C code

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=4056e774b1b3b07db83fcf3dea2e62d0bf02cd9b

commit 4056e774b1b3b07db83fcf3dea2e62d0bf02cd9b
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2024-12-11 15:48:56 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2024-12-11 17:02:24 +0000

    arm64: Move setting TCR_HD to C code
    
    To allow for it to be more selective when we enable it, e.g. if the
    CPU has an erratum that prevents us from doing so, move the check for
    setting TCR_HD to C.
    
    Reviewed by:    alc
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D47808
---
 sys/arm64/arm64/locore.S     | 17 +++++++----------
 sys/arm64/arm64/mp_machdep.c |  1 +
 sys/arm64/arm64/pmap.c       | 21 +++++++++++++++++++++
 sys/arm64/include/pmap.h     |  1 +
 4 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index f9a179931d7d..e721092455e8 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -940,20 +940,17 @@ LENTRY(start_mmu)
 	bfi	x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
 
 	/*
-	 * Check if the HW supports access flag and dirty state updates,
-	 * and set TCR_EL1.HA and TCR_EL1.HD accordingly.
+	 * Check if the HW supports access flag updates, and set
+	 * TCR_EL1.HA accordingly. The TCR_EL1.HD flag to enable
+	 * HW management of dirty state is set in C code as it may
+	 * need to be disabled because of CPU errata.
 	 */
 	mrs	x3, id_aa64mmfr1_el1
 	and	x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK)
-	cmp	x3, #1
-	b.ne	1f
-	orr 	x2, x2, #(TCR_HA)
-	b	2f
+	cbz	x3, 1f
+	orr	x2, x2, #(TCR_HA)
 1:
-	cmp	x3, #2
-	b.ne	2f
-	orr 	x2, x2, #(TCR_HA | TCR_HD)
-2:
+
 	msr	tcr_el1, x2
 
 	/*
diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c
index e9b015443477..636f26fba939 100644
--- a/sys/arm64/arm64/mp_machdep.c
+++ b/sys/arm64/arm64/mp_machdep.c
@@ -219,6 +219,7 @@ init_secondary(uint64_t cpu)
 	pcpup = cpuid_to_pcpu[cpu];
 	pcpup->pc_midr = get_midr();
 	identify_cpu(cpu);
+	pmap_cpu_init();
 
 	/* Ensure the stores in identify_cpu have completed */
 	atomic_thread_fence_acq_rel();
diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c
index 17e34888282a..b8f519388977 100644
--- a/sys/arm64/arm64/pmap.c
+++ b/sys/arm64/arm64/pmap.c
@@ -1309,6 +1309,8 @@ pmap_bootstrap(vm_size_t kernlen)
 	vm_paddr_t start_pa, pa;
 	uint64_t tcr;
 
+	pmap_cpu_init();
+
 	tcr = READ_SPECIALREG(tcr_el1);
 
 	/* Verify that the ASID is set through TTBR0. */
@@ -1623,6 +1625,25 @@ pmap_init_pv_table(void)
 	}
 }
 
+void
+pmap_cpu_init(void)
+{
+	uint64_t id_aa64mmfr1, tcr;
+
+	/* Enable HAFDBS if supported */
+	id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
+	if (ID_AA64MMFR1_HAFDBS_VAL(id_aa64mmfr1) >=ID_AA64MMFR1_HAFDBS_AF_DBS){
+		tcr = READ_SPECIALREG(tcr_el1) | TCR_HD;
+		WRITE_SPECIALREG(tcr_el1, tcr);
+		isb();
+		/* Flush the local TLB for the TCR_HD flag change */
+		dsb(nshst);
+		__asm __volatile("tlbi vmalle1");
+		dsb(nsh);
+		isb();
+	}
+}
+
 /*
  *	Initialize the pmap module.
  *
diff --git a/sys/arm64/include/pmap.h b/sys/arm64/include/pmap.h
index 8bdb4cf025e3..d92069ee42fd 100644
--- a/sys/arm64/include/pmap.h
+++ b/sys/arm64/include/pmap.h
@@ -140,6 +140,7 @@ extern pt_entry_t pmap_sh_attr;
 
 void	pmap_activate_vm(pmap_t);
 void	pmap_bootstrap(vm_size_t);
+void	pmap_cpu_init(void);
 int	pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
 int	pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot);
 void	pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode);