git: 8f7835acc6d6 - main - Remove SOC FPGA drivers
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Date: Fri, 06 Dec 2024 22:39:34 UTC
The branch main has been updated by jhb:
URL: https://cgit.FreeBSD.org/src/commit/?id=8f7835acc6d6d39854a82173d4cf10695c6eea13
commit 8f7835acc6d6d39854a82173d4cf10695c6eea13
Author: John Baldwin <jhb@FreeBSD.org>
AuthorDate: 2024-12-06 22:38:52 +0000
Commit: John Baldwin <jhb@FreeBSD.org>
CommitDate: 2024-12-06 22:38:52 +0000
Remove SOC FPGA drivers
The drivers have been disconnected from the build since the removal of
the SOCFPGA kernel configs.
Reviewed by: manu, imp, andrew
Sponsored by: AFRL, DARPA
Differential Revision: https://reviews.freebsd.org/D47885
---
ObsoleteFiles.inc | 8 +
share/man/man4/Makefile | 6 -
share/man/man4/altera_atse.4 | 117 --
share/man/man4/altera_avgen.4 | 153 --
share/man/man4/altera_jtag_uart.4 | 119 --
share/man/man4/altera_sdcard.4 | 116 --
sys/arm/altera/socfpga/files.socfpga | 18 -
sys/arm/altera/socfpga/socfpga_a10_manager.c | 437 ------
sys/arm/altera/socfpga/socfpga_common.c | 41 -
sys/arm/altera/socfpga/socfpga_common.h | 36 -
sys/arm/altera/socfpga/socfpga_l3regs.h | 52 -
sys/arm/altera/socfpga/socfpga_machdep.c | 173 ---
sys/arm/altera/socfpga/socfpga_manager.c | 426 ------
sys/arm/altera/socfpga/socfpga_mp.c | 230 ---
sys/arm/altera/socfpga/socfpga_mp.h | 33 -
sys/arm/altera/socfpga/socfpga_rstmgr.c | 255 ----
sys/arm/altera/socfpga/socfpga_rstmgr.h | 48 -
sys/arm/altera/socfpga/std.socfpga | 6 -
sys/conf/files | 12 -
sys/conf/options | 7 -
sys/dev/altera/atse/if_atse.c | 1592 --------------------
sys/dev/altera/atse/if_atse_fdt.c | 144 --
sys/dev/altera/atse/if_atse_nexus.c | 158 --
sys/dev/altera/atse/if_atsereg.h | 464 ------
sys/dev/altera/avgen/altera_avgen.c | 551 -------
sys/dev/altera/avgen/altera_avgen.h | 96 --
sys/dev/altera/avgen/altera_avgen_fdt.c | 159 --
sys/dev/altera/avgen/altera_avgen_nexus.c | 141 --
sys/dev/altera/jtag_uart/altera_jtag_uart.h | 197 ---
sys/dev/altera/jtag_uart/altera_jtag_uart_cons.c | 331 ----
sys/dev/altera/jtag_uart/altera_jtag_uart_fdt.c | 148 --
sys/dev/altera/jtag_uart/altera_jtag_uart_nexus.c | 139 --
sys/dev/altera/jtag_uart/altera_jtag_uart_tty.c | 561 -------
sys/dev/altera/msgdma/msgdma.c | 637 --------
sys/dev/altera/msgdma/msgdma.h | 148 --
sys/dev/altera/pio/pio.c | 208 ---
sys/dev/altera/pio/pio.h | 40 -
sys/dev/altera/pio/pio_if.m | 64 -
sys/dev/altera/sdcard/altera_sdcard.c | 412 -----
sys/dev/altera/sdcard/altera_sdcard.h | 247 ---
sys/dev/altera/sdcard/altera_sdcard_disk.c | 184 ---
sys/dev/altera/sdcard/altera_sdcard_fdt.c | 121 --
sys/dev/altera/sdcard/altera_sdcard_io.c | 446 ------
sys/dev/altera/sdcard/altera_sdcard_nexus.c | 112 --
sys/dev/altera/softdma/a_api.h | 98 --
sys/dev/altera/softdma/softdma.c | 882 -----------
sys/dev/beri/beri_mem.c | 181 ---
sys/dev/beri/beri_ring.c | 524 -------
sys/dev/beri/virtio/network/if_vtbe.c | 648 --------
sys/dev/beri/virtio/virtio.c | 261 ----
sys/dev/beri/virtio/virtio.h | 69 -
sys/dev/beri/virtio/virtio_block.c | 553 -------
sys/dev/beri/virtio/virtio_mmio_platform.c | 307 ----
sys/dev/beri/virtio/virtio_mmio_platform.h | 35 -
sys/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts | 151 --
tools/kerneldoc/subsys/Doxyfile-dev_altera | 19 -
tools/kerneldoc/subsys/Doxyfile-dev_beri | 19 -
57 files changed, 8 insertions(+), 13332 deletions(-)
diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc
index 5362ba0e5955..a59907a36969 100644
--- a/ObsoleteFiles.inc
+++ b/ObsoleteFiles.inc
@@ -51,6 +51,14 @@
# xargs -n1 | sort | uniq -d;
# done
+# 2024xxxx: Remove Altera DE4 drivers
+OLD_FILES+=usr/share/man/man4/altera_atse.4.gz
+OLD_FILES+=usr/share/man/man4/altera_avgen.4.gz
+OLD_FILES+=usr/share/man/man4/altera_jtag_uart.4.gz
+OLD_FILES+=usr/share/man/man4/altera_sdcard.4.gz
+OLD_FILES+=usr/share/man/man4/altera_sdcardc.4.gz
+OLD_FILES+=usr/share/man/man4/atse.4.gz
+
# 20241124: library and tests of OpenBSD dc
OLD_FILES+=usr/share/misc/bc.library
OLD_FILES+=usr/tests/usr.bin/dc/Kyuafile
diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile
index 0f3e72007e7c..a7dbf6c615d6 100644
--- a/share/man/man4/Makefile
+++ b/share/man/man4/Makefile
@@ -38,10 +38,6 @@ MAN= aac.4 \
alc.4 \
ale.4 \
alpm.4 \
- altera_atse.4 \
- altera_avgen.4 \
- altera_jtag_uart.4 \
- altera_sdcard.4 \
altq.4 \
amdpm.4 \
${_amdsbwd.4} \
@@ -651,8 +647,6 @@ MLINKS+=age.4 if_age.4
MLINKS+=agp.4 agpgart.4
MLINKS+=alc.4 if_alc.4
MLINKS+=ale.4 if_ale.4
-MLINKS+=altera_atse.4 atse.4
-MLINKS+=altera_sdcard.4 altera_sdcardc.4
MLINKS+=altq.4 ALTQ.4
MLINKS+=ath.4 if_ath.4
MLINKS+=aue.4 if_aue.4
diff --git a/share/man/man4/altera_atse.4 b/share/man/man4/altera_atse.4
deleted file mode 100644
index d425b125d961..000000000000
--- a/share/man/man4/altera_atse.4
+++ /dev/null
@@ -1,117 +0,0 @@
-.\"-
-.\" Copyright (c) 2013-2014 SRI International
-.\" All rights reserved.
-.\"
-.\" This software was developed by SRI International and the University of
-.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
-.\" ("CTSRD"), as part of the DARPA CRASH research programme.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\" notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\" notice, this list of conditions and the following disclaimer in the
-.\" documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.Dd May 21, 2014
-.Dt ALTERA_ATSE 4
-.Os
-.Sh NAME
-.Nm atse
-.Nd driver for the Altera Triple-Speed Ethernet MegaCore
-.Sh SYNOPSIS
-.Cd "device atse"
-.Cd "options ATSE_CFI_HACK"
-.Pp
-In
-.Pa /boot/device.hints :
-.Cd hint.atse.0.at="nexus0"
-.Cd hint.atse.0.maddr=0x7f007000
-.Cd hint.atse.0.msize=0x540
-.Cd hint.atse.0.rc_irq=1
-.Cd hint.atse.0.rx_maddr=0x7f007500
-.Cd hint.atse.0.rx_msize=0x8
-.Cd hint.atse.0.rxc_maddr=0x7f007520
-.Cd hint.atse.0.rxc_msize=0x20
-.Cd hint.atse.0.tx_irq=2
-.Cd hint.atse.0.tx_maddr=0x7f007400
-.Cd hint.atse.0.tx_msize=0x8
-.Cd hint.atse.0.txc_maddr=0x7f007420
-.Cd hint.atse.0.txc_msize=0x20
-.Cd hint.e1000phy.0.at="miibus0"
-.Cd hint.e1000phy.0.phyno=0
-.Sh DESCRIPTION
-The
-.Nm
-device driver provides support for the Altera Triple-Speed Ethernet
-MegaCore.
-.Sh HARDWARE
-The current version of the
-.Nm
-driver supports the Ethernet MegaCore as described in version 11.1 of
-Altera's documentation when the device is configured with internal FIFOs.
-.Sh MAC SELECTION
-The default MAC address for each
-.Nm
-interface is derived from a value stored in
-.Xr cfi 4
-flash.
-The value is managed by the
-.Xr atsectl 8
-utility.
-.Pp
-Only a single MAC address may be stored in flash.
-If the address begins with the Altera prefix 00:07:ed and ends in 00 then
-up to 16 addresses will be derived from it by adding the unit number of
-the interface to the stored address.
-For other prefixes, the address will be assigned to atse0 and random
-addresses will be used for other interfaces.
-If the stored address is invalid, for example all zero's, multicast, or the
-default address shipped on all DE4 boards (00:07:ed:ff:ed:15) then a random
-address is generated when the device is attached.
-.Sh SEE ALSO
-.Xr miibus 4 ,
-.Xr netintro 4 ,
-.Xr ifconfig 8
-.Rs
-.%T Triple-Speed Ethernet MegaCore Function User Guide
-.%D November 2011
-.%I Altera Corporation
-.Re
-.Sh HISTORY
-The
-.Nm
-device driver first appeared in
-.Fx 10.0 .
-.Sh AUTHORS
-The
-.Nm
-device driver and this manual page were
-developed by SRI International and the University of Cambridge Computer
-Laboratory under DARPA/AFRL contract
-.Pq FA8750-10-C-0237
-.Pq Do CTSRD Dc ,
-as part of the DARPA CRASH research programme.
-This device driver was written by
-.An Bjoern A. Zeeb .
-.Sh BUGS
-The
-.Nm
-driver only supports a single configuration of the MegaCore as installed
-on the Terasic Technologies Altera DE4 Development and Education Board.
-.Pp
-Only gigabit Ethernet speeds are currently supported.
diff --git a/share/man/man4/altera_avgen.4 b/share/man/man4/altera_avgen.4
deleted file mode 100644
index dc7e9a0a308b..000000000000
--- a/share/man/man4/altera_avgen.4
+++ /dev/null
@@ -1,153 +0,0 @@
-.\"-
-.\" Copyright (c) 2012 Robert N. M. Watson
-.\" All rights reserved.
-.\"
-.\" This software was developed by SRI International and the University of
-.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
-.\" ("CTSRD"), as part of the DARPA CRASH research programme.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\" notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\" notice, this list of conditions and the following disclaimer in the
-.\" documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.Dd August 18, 2012
-.Dt ALTERA_AVGEN 4
-.Os
-.Sh NAME
-.Nm altera_avgen
-.Nd driver for generic Altera Avalon-bus-attached, memory-mapped devices
-.Sh SYNOPSIS
-.Cd "device altera_avgen"
-.Pp
-In
-.Pa /boot/device.hints :
-.Cd hint.altera_avgen.0.at="nexus0"
-.Cd hint.altera_avgen.0.maddr=0x7f00a000
-.Cd hint.altera_avgen.0.msize=20
-.Cd hint.altera_avgen.0.width=4
-.Cd hint.altera_avgen.0.fileio="rw"
-.Cd hint.altera_avgen.0.devname="berirom"
-.Sh DESCRIPTION
-The
-.Nm
-device driver provides generic support for memory-mapped devices on the
-Altera Avalon bus.
-.Pa device.hints
-entries configure the address, size, I/O disposition, and
-.Pa /dev
-device node name that will be used.
-The
-.Xr open 2 ,
-.Xr read 2 ,
-.Xr write 2 ,
-and
-.Xr mmap 2
-system calls (and variations) may be used on
-.Nm
-device nodes, subject to constraints imposed using
-.Pa device.hints
-entries.
-Although reading and writing mapped memory is supported,
-.Nm
-does not currently support directing device interrupts to userspace.
-.Pp
-A number of
-.Pa device.hints
-sub-fields are available to configure
-.Nm
-device instances:
-.Bl -tag -width devunit
-.It maddr
-base physical address of the memory region to export; must be aligned to
-.Li width
-.It msize
-length of the memory region export; must be aligned to
-.Li width
-.It width
-Granularity at which
-.Xr read 2
-and
-.Xr write 2
-operations will be performed.
-Larger requests will be broken down into
-.Li width -sized
-operations; smaller requests will be rejected.
-I/O operations must be aligned to
-.Li width .
-.It fileio
-allowed file descriptor operations;
-.Li r
-authorizes
-.Xr read 2 ;
-.Li w
-authorizes
-.Xr write 2 .
-.It mmapio
-allowed
-.Xr mmap 2
-permissions;
-.Li w
-authorizes
-.Dv PROT_WRITE ;
-.Li r
-authorizes
-.Dv PROT_READ ;
-.Li x
-authorizes
-.Dv PROT_EXEC .
-.It devname
-specifies a device name relative to
-.Pa /dev .
-.It devunit
-specifies a device unit number; no unit number is used if this is unspecified.
-.El
-.Sh SEE ALSO
-.Xr mmap 2 ,
-.Xr open 2 ,
-.Xr read 2 ,
-.Xr write 2
-.Sh HISTORY
-The
-.Nm
-device driver first appeared in
-.Fx 10.0 .
-.Sh AUTHORS
-The
-.Nm
-device driver and this manual page were
-developed by SRI International and the University of Cambridge Computer
-Laboratory under DARPA/AFRL contract
-.Pq FA8750-10-C-0237
-.Pq Do CTSRD Dc ,
-as part of the DARPA CRASH research programme.
-This device driver was written by
-.An Robert N. M. Watson .
-.Sh BUGS
-.Nm
-is intended to support the writing of userspace device drivers; however, it
-does not permit directing interrupts to userspace, only memory-mapped I/O.
-.Pp
-.Nm
-supports only a
-.Li nexus
-bus attachment, which is appropriate for system-on-chip busses such as
-Altera's Avalon bus.
-If the target device is off of another bus type, then additional bus
-attachments will be required.
diff --git a/share/man/man4/altera_jtag_uart.4 b/share/man/man4/altera_jtag_uart.4
deleted file mode 100644
index 339e58d7c2f1..000000000000
--- a/share/man/man4/altera_jtag_uart.4
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"-
-.\" Copyright (c) 2012 Robert N. M. Watson
-.\" All rights reserved.
-.\"
-.\" This software was developed by SRI International and the University of
-.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
-.\" ("CTSRD"), as part of the DARPA CRASH research programme.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\" notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\" notice, this list of conditions and the following disclaimer in the
-.\" documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.Dd August 18, 2012
-.Dt ALTERA_JTAG_UART 4
-.Os
-.Sh NAME
-.Nm altera_jtag_uart
-.Nd driver for the Altera JTAG UART Core
-.Sh SYNOPSIS
-.Cd "device altera_jtag_uart"
-.Pp
-In
-.Pa /boot/device.hints :
-.Cd hint.altera_jtag_uart.0.at="nexus0"
-.Cd hint.altera_jtag_uart.0.maddr=0x7f000000
-.Cd hint.altera_jtag_uart.0.msize=0x40
-.Cd hint.altera_jtag_uart.0.irq=0
-.Cd hint.altera_jtag_uart.1.at="nexus0"
-.Cd hint.altera_jtag_uart.1.maddr=0x7f001000
-.Cd hint.altera_jtag_uart.1.msize=0x40
-.Sh DESCRIPTION
-The
-.Nm
-device driver provides support for the Altera JTAG UART core, which allows
-multiple UART-like streams to be carried over JTAG.
-.Nm
-allows JTAG UART streams to be attached to both the low-level console
-interface, used for direct kernel input and output, and the
-.Xr tty 4
-layer, to be used with
-.Xr ttys 5
-and
-.Xr login 1 .
-Sequential Altera JTAG UART devices will appear as
-.Li ttyu0 ,
-.Li ttyu1 ,
-etc.
-.Sh HARDWARE
-Altera JTAG UART devices can be connected to using Altera's
-.Pa nios2-terminal
-program, with the instance selected using the
-.Li --instance
-argument on the management host.
-.Nm
-supports JTAG UART cores with or without interrupt lines connected; if the
-.Li irq
-portion of the
-.Pa device.hints
-entry is omitted, the driver will poll rather than configure interrupts.
-.Sh SEE ALSO
-.Xr login 1 ,
-.Xr tty 4 ,
-.Xr ttys 5
-.Rs
-.%T Altera Embedded Peripherals IP User Guide
-.%D June 2011
-.%I Altera Corporation
-.%U http://www.altera.com/literature/ug/ug_embedded_ip.pdf
-.Re
-.Sh HISTORY
-The
-.Nm
-device driver first appeared in
-.Fx 10.0 .
-.Sh AUTHORS
-The
-.Nm
-device driver and this manual page were
-developed by SRI International and the University of Cambridge Computer
-Laboratory under DARPA/AFRL contract
-.Pq FA8750-10-C-0237
-.Pq Do CTSRD Dc ,
-as part of the DARPA CRASH research programme.
-This device driver was written by
-.An Robert N. M. Watson .
-.Sh BUGS
-.Nm
-must dynamically poll to detect when JTAG is present, in order to disable flow
-control in the event that there is no receiving endpoint.
-Otherwise, the boot may hang waiting for the JTAG client to be attached, and
-user processes attached to JTAG UART devices might block indefinitely.
-However, there is no way to flush the output buffer once JTAG is detected to
-have disappeared; this means that a small amount of stale output data will
-remain in the output buffer, being displayed by
-.Li nios2-terminal
-when it is connected.
-Loss of JTAG will not generate a hang-up event, as that is rarely the desired
-behaviour.
-.Pp
-.Li nios2-terminal
-does not place the client-side TTY in raw mode, and so by default will not
-pass all control characters through to the UART.
diff --git a/share/man/man4/altera_sdcard.4 b/share/man/man4/altera_sdcard.4
deleted file mode 100644
index 65d1ba5369ed..000000000000
--- a/share/man/man4/altera_sdcard.4
+++ /dev/null
@@ -1,116 +0,0 @@
-.\"-
-.\" Copyright (c) 2012 Robert N. M. Watson
-.\" All rights reserved.
-.\"
-.\" This software was developed by SRI International and the University of
-.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
-.\" ("CTSRD"), as part of the DARPA CRASH research programme.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\" notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\" notice, this list of conditions and the following disclaimer in the
-.\" documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.Dd August 18, 2012
-.Dt ALTERA_SDCARD 4
-.Os
-.Sh NAME
-.Nm altera_sdcard
-.Nd driver for the Altera University Program Secure Data Card IP Core
-.Sh SYNOPSIS
-.Cd "device altera_sdcard"
-.Pp
-In
-.Pa /boot/device.hints :
-.Cd hint.altera_sdcardc.0.at="nexus0"
-.Cd hint.altera_sdcardc.0.maddr=0x7f008000
-.Cd hint.altera_sdcardc.0.msize=0x400
-.Sh DESCRIPTION
-The
-.Nm
-device driver provides support for the Altera University Program Secure Data
-Card (SD Card) IP Core device.
-A controller device,
-.Li altera_sdcardcX ,
-will be attached during boot.
-Inserted disks are presented as
-.Xr disk 9
-devices,
-.Li altera_sdcardX ,
-corresponding to the controller number.
-.Sh HARDWARE
-The current version of the
-.Nm
-driver supports the SD Card IP core as described in the August 2011 version of
-Altera's documentation.
-The core supports only cards up to 2G (CSD 0); larger cards, or cards using
-newer CSD versions, will not be detected.
-The IP core has two key limitations: a lack of interrupt support, requiring
-timer-driven polling to detect I/O completion, and support for only single
-512-byte block read and write operations at a time.
-The combined effect of those two limits is that the system clock rate,
-.Dv HZ ,
-must be set to at least 200 in order to accomplish the maximum 100KB/s data
-rate supported by the IP core.
-.Sh SEE ALSO
-.Xr disk 9
-.Rs
-.%T Altera University Program Secure Data Card IP Core
-.%D August 2011
-.%I Altera Corporation - University Program
-.%U ftp://ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/SD_Card_Interface_for_SoPC_Builder.pdf
-.Re
-.Sh HISTORY
-The
-.Nm
-device driver first appeared in
-.Fx 10.0 .
-.Sh AUTHORS
-The
-.Nm
-device driver and this manual page were
-developed by SRI International and the University of Cambridge Computer
-Laboratory under DARPA/AFRL contract
-.Pq FA8750-10-C-0237
-.Pq Do CTSRD Dc ,
-as part of the DARPA CRASH research programme.
-This device driver was written by
-.An Robert N. M. Watson .
-.Sh BUGS
-.Nm
-contains a number of work-arounds for IP core bugs.
-Perhaps most critically,
-.Nm
-ignores the CRC error bit returned in the RR1 register, which appears to be
-unexpectedly set by the IP core.
-.Pp
-.Nm
-uses fixed polling intervals are used for card insertion/removal and
-I/O completion detection; an adaptive strategy might improve performance by
-reducing the latency to detecting completed I/O.
-However, in our experiments, using polling rates greater than 200 times a
-second did not improve performance.
-.Pp
-.Nm
-supports only a
-.Li nexus
-bus attachment, which is appropriate for system-on-chip busses such as
-Altera's Avalon bus.
-If the IP core is configured off of another bus type, then additional bus
-attachments will be required.
diff --git a/sys/arm/altera/socfpga/files.socfpga b/sys/arm/altera/socfpga/files.socfpga
deleted file mode 100644
index 1cf8d95b9fa3..000000000000
--- a/sys/arm/altera/socfpga/files.socfpga
+++ /dev/null
@@ -1,18 +0,0 @@
-
-arm/altera/socfpga/socfpga_common.c standard
-arm/altera/socfpga/socfpga_machdep.c standard
-arm/altera/socfpga/socfpga_manager.c standard
-arm/altera/socfpga/socfpga_rstmgr.c standard
-arm/altera/socfpga/socfpga_mp.c optional smp
-
-dev/mmc/host/dwmmc_altera.c optional dwmmc
-
-# Arria 10
-arm/altera/socfpga/socfpga_a10_manager.c standard
-
-# BERI specific
-dev/beri/beri_ring.c optional beri_ring
-dev/beri/beri_mem.c optional beri_mem
-dev/beri/virtio/virtio.c optional beri_vtblk | vtbe
-dev/beri/virtio/virtio_block.c optional beri_vtblk
-dev/beri/virtio/network/if_vtbe.c optional vtbe
diff --git a/sys/arm/altera/socfpga/socfpga_a10_manager.c b/sys/arm/altera/socfpga/socfpga_a10_manager.c
deleted file mode 100644
index 01267bcaacf1..000000000000
--- a/sys/arm/altera/socfpga/socfpga_a10_manager.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/*-
- * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Intel Arria 10 FPGA Manager.
- * Chapter 4, Arria 10 Hard Processor System Technical Reference Manual.
- * Chapter A, FPGA Reconfiguration.
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <sys/timeet.h>
-#include <sys/timetc.h>
-#include <sys/conf.h>
-#include <sys/uio.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/intr.h>
-
-#include <arm/altera/socfpga/socfpga_common.h>
-
-#define FPGAMGR_DCLKCNT 0x8 /* DCLK Count Register */
-#define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */
-#define FPGAMGR_GPO 0x10 /* General-Purpose Output Register */
-#define FPGAMGR_GPI 0x14 /* General-Purpose Input Register */
-#define FPGAMGR_MISCI 0x18 /* Miscellaneous Input Register */
-#define IMGCFG_CTRL_00 0x70
-#define S2F_CONDONE_OE (1 << 24)
-#define S2F_NSTATUS_OE (1 << 16)
-#define CTRL_00_NCONFIG (1 << 8)
-#define CTRL_00_NENABLE_CONDONE (1 << 2)
-#define CTRL_00_NENABLE_NSTATUS (1 << 1)
-#define CTRL_00_NENABLE_NCONFIG (1 << 0)
-#define IMGCFG_CTRL_01 0x74
-#define CTRL_01_S2F_NCE (1 << 24)
-#define CTRL_01_S2F_PR_REQUEST (1 << 16)
-#define CTRL_01_S2F_NENABLE_CONFIG (1 << 0)
-#define IMGCFG_CTRL_02 0x78
-#define CTRL_02_CDRATIO_S 16
-#define CTRL_02_CDRATIO_M (0x3 << CTRL_02_CDRATIO_S)
-#define CTRL_02_CFGWIDTH_16 (0 << 24)
-#define CTRL_02_CFGWIDTH_32 (1 << 24)
-#define CTRL_02_EN_CFG_DATA (1 << 8)
-#define CTRL_02_EN_CFG_CTRL (1 << 0)
-#define IMGCFG_STAT 0x80
-#define F2S_PR_ERROR (1 << 11)
-#define F2S_PR_DONE (1 << 10)
-#define F2S_PR_READY (1 << 9)
-#define F2S_MSEL_S 16
-#define F2S_MSEL_M (0x7 << F2S_MSEL_S)
-#define MSEL_PASSIVE_FAST 0
-#define MSEL_PASSIVE_SLOW 1
-#define F2S_NCONFIG_PIN (1 << 12)
-#define F2S_CONDONE_OE (1 << 7)
-#define F2S_NSTATUS_PIN (1 << 4)
-#define F2S_CONDONE_PIN (1 << 6)
-#define F2S_USERMODE (1 << 2)
-
-struct fpgamgr_a10_softc {
- struct resource *res[2];
- bus_space_tag_t bst_data;
- bus_space_handle_t bsh_data;
- struct cdev *mgr_cdev;
- device_t dev;
-};
-
-static struct resource_spec fpgamgr_a10_spec[] = {
- { SYS_RES_MEMORY, 0, RF_ACTIVE },
- { SYS_RES_MEMORY, 1, RF_ACTIVE },
- { -1, 0 }
-};
-
-static int
-fpga_wait_dclk_pulses(struct fpgamgr_a10_softc *sc, int npulses)
-{
- int tout;
-
- /* Clear done bit, if any */
- if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
- WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
-
- /* Request DCLK pulses */
- WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
-
- /* Wait finish */
- tout = 1000;
- while (tout > 0) {
- if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
- WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
- break;
- }
- tout--;
- DELAY(10);
- }
- if (tout == 0) {
- device_printf(sc->dev,
- "Error: dclkpulses wait timeout\n");
- return (1);
- }
-
- return (0);
-}
-
-static int
-fpga_open(struct cdev *dev, int flags __unused,
- int fmt __unused, struct thread *td __unused)
-{
- struct fpgamgr_a10_softc *sc;
- int tout;
- int msel;
- int reg;
-
- sc = dev->si_drv1;
-
- /* Step 1 */
- reg = READ4(sc, IMGCFG_STAT);
- if ((reg & F2S_USERMODE) == 0) {
- device_printf(sc->dev, "Error: invalid mode\n");
- return (ENXIO);
- };
-
- /* Step 2 */
- reg = READ4(sc, IMGCFG_STAT);
- msel = (reg & F2S_MSEL_M) >> F2S_MSEL_S;
- if ((msel != MSEL_PASSIVE_FAST) && \
- (msel != MSEL_PASSIVE_SLOW)) {
- device_printf(sc->dev,
- "Error: invalid msel %d\n", msel);
- return (ENXIO);
- };
-
- /*
- * Step 3.
- * TODO: add support for compressed, encrypted images.
- */
- reg = READ4(sc, IMGCFG_CTRL_02);
- reg &= ~(CTRL_02_CDRATIO_M);
- WRITE4(sc, IMGCFG_CTRL_02, reg);
-
- reg = READ4(sc, IMGCFG_CTRL_02);
- reg &= ~CTRL_02_CFGWIDTH_32;
- WRITE4(sc, IMGCFG_CTRL_02, reg);
-
- /* Step 4. a */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg &= ~CTRL_01_S2F_PR_REQUEST;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- reg = READ4(sc, IMGCFG_CTRL_00);
- reg |= CTRL_00_NCONFIG;
- WRITE4(sc, IMGCFG_CTRL_00, reg);
-
- /* b */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg &= ~CTRL_01_S2F_NCE;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- /* c */
- reg = READ4(sc, IMGCFG_CTRL_02);
- reg |= CTRL_02_EN_CFG_CTRL;
- WRITE4(sc, IMGCFG_CTRL_02, reg);
-
- /* d */
- reg = READ4(sc, IMGCFG_CTRL_00);
- reg &= ~S2F_CONDONE_OE;
- reg &= ~S2F_NSTATUS_OE;
- reg |= CTRL_00_NCONFIG;
- reg |= CTRL_00_NENABLE_NSTATUS;
- reg |= CTRL_00_NENABLE_CONDONE;
- reg &= ~CTRL_00_NENABLE_NCONFIG;
- WRITE4(sc, IMGCFG_CTRL_00, reg);
-
- /* Step 5 */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg &= ~CTRL_01_S2F_NENABLE_CONFIG;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- /* Step 6 */
- fpga_wait_dclk_pulses(sc, 0x100);
-
- /* Step 7. a */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg |= CTRL_01_S2F_PR_REQUEST;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- /* b, c */
- fpga_wait_dclk_pulses(sc, 0x7ff);
-
- /* Step 8 */
- tout = 10;
- while (tout--) {
- reg = READ4(sc, IMGCFG_STAT);
- if (reg & F2S_PR_ERROR) {
- device_printf(sc->dev,
- "Error: PR failed on open.\n");
- return (ENXIO);
- }
- if (reg & F2S_PR_READY) {
- break;
- }
- }
- if (tout == 0) {
- device_printf(sc->dev,
- "Error: Timeout waiting PR ready bit.\n");
- return (ENXIO);
- }
-
- return (0);
-}
-
-static int
-fpga_close(struct cdev *dev, int flags __unused,
- int fmt __unused, struct thread *td __unused)
-{
- struct fpgamgr_a10_softc *sc;
- int tout;
- int reg;
-
- sc = dev->si_drv1;
-
- /* Step 10 */
- tout = 10;
- while (tout--) {
- reg = READ4(sc, IMGCFG_STAT);
- if (reg & F2S_PR_ERROR) {
- device_printf(sc->dev,
- "Error: PR failed.\n");
- return (ENXIO);
- }
- if (reg & F2S_PR_DONE) {
- break;
- }
- }
-
- /* Step 11 */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg &= ~CTRL_01_S2F_PR_REQUEST;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- /* Step 12, 13 */
- fpga_wait_dclk_pulses(sc, 0x100);
-
- /* Step 14 */
- reg = READ4(sc, IMGCFG_CTRL_02);
- reg &= ~CTRL_02_EN_CFG_CTRL;
- WRITE4(sc, IMGCFG_CTRL_02, reg);
-
- /* Step 15 */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg |= CTRL_01_S2F_NCE;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- /* Step 16 */
- reg = READ4(sc, IMGCFG_CTRL_01);
- reg |= CTRL_01_S2F_NENABLE_CONFIG;
- WRITE4(sc, IMGCFG_CTRL_01, reg);
-
- /* Step 17 */
- reg = READ4(sc, IMGCFG_STAT);
- if ((reg & F2S_USERMODE) == 0) {
- device_printf(sc->dev,
- "Error: invalid mode\n");
- return (ENXIO);
- };
-
- if ((reg & F2S_CONDONE_PIN) == 0) {
- device_printf(sc->dev,
- "Error: configuration not done\n");
- return (ENXIO);
- };
*** 12807 LINES SKIPPED ***