git: e3bd5730ca92 - main - bhyve: Extract uart-clock from fdt_add_uart as an apb-pclk

The branch main has been updated by markj:

URL: https://cgit.FreeBSD.org/src/commit/?id=e3bd5730ca925cd74dece9c52bcc10237b058546

commit e3bd5730ca925cd74dece9c52bcc10237b058546
Author:     Jessica Clarke <jrtc27@jrtc27.com>
AuthorDate: 2024-02-21 22:44:57 +0000
Commit:     Mark Johnston <markj@FreeBSD.org>
CommitDate: 2024-04-10 15:17:56 +0000

    bhyve: Extract uart-clock from fdt_add_uart as an apb-pclk
    
    This clock will also be used by the PL031 RTC (rather than defining
    redundant per-device clocks).
    
    Reviewed by:    jhb
    MFC after:      2 weeks
    Obtained from:  CheriBSD
---
 usr.sbin/bhyve/aarch64/fdt.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/usr.sbin/bhyve/aarch64/fdt.c b/usr.sbin/bhyve/aarch64/fdt.c
index 65876f0f90e8..e8c959a65f3b 100644
--- a/usr.sbin/bhyve/aarch64/fdt.c
+++ b/usr.sbin/bhyve/aarch64/fdt.c
@@ -57,6 +57,7 @@
 
 static void *fdtroot;
 static uint32_t gic_phandle = 0;
+static uint32_t apb_pclk_phandle;
 
 static uint32_t
 assign_phandle(void *fdt)
@@ -155,6 +156,14 @@ fdt_init(struct vmctx *ctx, int ncpu, vm_paddr_t fdtaddr, vm_size_t fdtsize)
 	fdt_property_string(fdt, "method", "hvc");
 	fdt_end_node(fdt);
 
+	fdt_begin_node(fdt, "apb-pclk");
+	fdt_property_string(fdt, "compatible", "fixed-clock");
+	fdt_property_string(fdt, "clock-output-names", "clk24mhz");
+	fdt_property_u32(fdt, "#clock-cells", 0);
+	fdt_property_u32(fdt, "clock-frequency", 24000000);
+	apb_pclk_phandle = assign_phandle(fdt);
+	fdt_end_node(fdt);
+
 	/* Finalized by fdt_finalized(). */
 	fdtroot = fdt;
 
@@ -204,21 +213,13 @@ fdt_add_uart(uint64_t uart_base, uint64_t uart_size, int intr)
 {
 	void *fdt, *interrupts, *prop;
 	char node_name[32];
-	uint32_t clk_phandle;
 
 	assert(gic_phandle != 0);
+	assert(apb_pclk_phandle != 0);
 	assert(intr >= GIC_FIRST_SPI);
 
 	fdt = fdtroot;
 
-	fdt_begin_node(fdt, "uart-clock");
-	fdt_property_string(fdt, "compatible", "fixed-clock");
-	fdt_property_string(fdt, "clock-output-names", "clk24mhz");
-	fdt_property_u32(fdt, "#clock-cells", 0);
-	fdt_property_u32(fdt, "clock-frequency", 24000000);
-	clk_phandle = assign_phandle(fdt);
-	fdt_end_node(fdt);
-
 	snprintf(node_name, sizeof(node_name), "serial@%lx", uart_base);
 	fdt_begin_node(fdt, node_name);
 #define	UART_COMPAT	"arm,pl011\0arm,primecell"
@@ -232,8 +233,8 @@ fdt_add_uart(uint64_t uart_base, uint64_t uart_size, int intr)
 	SET_PROP_U32(interrupts, 1, intr - GIC_FIRST_SPI);
 	SET_PROP_U32(interrupts, 2, IRQ_TYPE_LEVEL_HIGH);
 	fdt_property_placeholder(fdt, "clocks", 2 * sizeof(uint32_t), &prop);
-	SET_PROP_U32(prop, 0, clk_phandle);
-	SET_PROP_U32(prop, 1, clk_phandle);
+	SET_PROP_U32(prop, 0, apb_pclk_phandle);
+	SET_PROP_U32(prop, 1, apb_pclk_phandle);
 #define	UART_CLK_NAMES	"uartclk\0apb_pclk"
 	fdt_property(fdt, "clock-names", UART_CLK_NAMES,
 	    sizeof(UART_CLK_NAMES));