git: 8ae54db63970 - main - arm64: rockchip: clk: Define PLIST macro in rk_cru.h

The branch main has been updated by manu:

URL: https://cgit.FreeBSD.org/src/commit/?id=8ae54db63970e9370d3d88f6eb57c102e085a128

commit 8ae54db63970e9370d3d88f6eb57c102e085a128
Author:     Emmanuel Vadot <manu@FreeBSD.org>
AuthorDate: 2023-09-19 15:59:34 +0000
Commit:     Emmanuel Vadot <manu@FreeBSD.org>
CommitDate: 2023-09-21 15:49:02 +0000

    arm64: rockchip: clk: Define PLIST macro in rk_cru.h
    
    We use it in all clock drivers so no need to define it everywhere
---
 sys/arm64/rockchip/clk/rk3288_cru.c | 1 -
 sys/arm64/rockchip/clk/rk3328_cru.c | 2 --
 sys/arm64/rockchip/clk/rk3399_cru.c | 1 -
 sys/arm64/rockchip/clk/rk_cru.h     | 4 ++++
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/sys/arm64/rockchip/clk/rk3288_cru.c b/sys/arm64/rockchip/clk/rk3288_cru.c
index cadb1f586a1a..e35481e94c13 100644
--- a/sys/arm64/rockchip/clk/rk3288_cru.c
+++ b/sys/arm64/rockchip/clk/rk3288_cru.c
@@ -525,7 +525,6 @@ static struct rk_clk_armclk_rates rk3288_armclk_rates[] = {
 	},								\
 }
 
-#define PLIST(_name) static const char *_name[]
 PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};
 PLIST(armclk_p)= {"apll_core", "gpll_core"};
 PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
diff --git a/sys/arm64/rockchip/clk/rk3328_cru.c b/sys/arm64/rockchip/clk/rk3328_cru.c
index f969c8d758a5..1f48ce6c23a2 100644
--- a/sys/arm64/rockchip/clk/rk3328_cru.c
+++ b/sys/arm64/rockchip/clk/rk3328_cru.c
@@ -636,8 +636,6 @@ static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = {
 };
 
 /* Clock parents */
-#define PLIST(_name) static const char *_name[]
-
 PLIST(pll_src_p) = {"xin24m"};
 PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"};
 
diff --git a/sys/arm64/rockchip/clk/rk3399_cru.c b/sys/arm64/rockchip/clk/rk3399_cru.c
index 3d43d832792f..3bff0e64ea34 100644
--- a/sys/arm64/rockchip/clk/rk3399_cru.c
+++ b/sys/arm64/rockchip/clk/rk3399_cru.c
@@ -695,7 +695,6 @@ static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {
 	},								\
 }
 
-#define PLIST(_name) static const char *_name[]
 PLIST(pll_src_p) = {"xin24m", "xin32k"};
 
 PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",
diff --git a/sys/arm64/rockchip/clk/rk_cru.h b/sys/arm64/rockchip/clk/rk_cru.h
index b00e987abcfa..55f230036199 100644
--- a/sys/arm64/rockchip/clk/rk_cru.h
+++ b/sys/arm64/rockchip/clk/rk_cru.h
@@ -42,6 +42,10 @@
 #include <arm64/rockchip/clk/rk_clk_pll.h>
 
 /* Macro for defining various types of clocks. */
+
+/* Parent list */
+#define PLIST(_name) static const char *_name[]
+
 /* Pure gate */
 #define	GATE(_idx, _clkname, _pname, _o, _s)				\
 {									\