From nobody Tue May 31 02:54:05 2022 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 10D821B5F19C; Tue, 31 May 2022 02:54:06 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4LBxgd7368z3R3t; Tue, 31 May 2022 02:54:05 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1653965646; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=sAuvFJ1fsrMUHTHS7gTv0KBeKWcfwkF6ylSIb1osbvw=; b=Y2v33KuTq3OHil1IMuvCHK2hFV2mAvCorLltWAXj8uHuQmJa/WFpih/Xw87VLjmaFEtjV+ SFfRc7LuhB1JhIGZ3i1P/gVIZ0pVMEoasG1dTOIN6prm9a6Gmjkud5tZGKRjWEZ+X2Afm/ OInIz+Xxeq5D0QmQFmPdCLEpoSc0+VjbLMP7yFq0oenjq3G3aDUpdxr59tJD3Rkootn+2O qofLi4tpWbzhM0LvaTAxRNw3f6mLxIwuPSzTjoa5rl1KG5OUwF/XDycDQ+/9noj9sYkc2D 7Oj/XNXRAqmNRtcVKBFe0WEzEhNT/BRtygJZoY+Vw7PbFFttKJNi56pWEAEmMQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D198D23881; Tue, 31 May 2022 02:54:05 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 24V2s5Rg061997; Tue, 31 May 2022 02:54:05 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 24V2s5qx061996; Tue, 31 May 2022 02:54:05 GMT (envelope-from git) Date: Tue, 31 May 2022 02:54:05 GMT Message-Id: <202205310254.24V2s5qx061996@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Alexander Motin Subject: git: ae57fbc7ec65 - main - hwpmc: Update Intel's programmable counters restrictions. List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mav X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: ae57fbc7ec65fcc75575a55c911e0da32ea9c20d Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1653965646; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=sAuvFJ1fsrMUHTHS7gTv0KBeKWcfwkF6ylSIb1osbvw=; b=PTZj9qRePPoFIY/SetkfKvaP7Bsc+BRGIPP6uCpcs1MOFYVFIsBj/mYk4VSQg5atVhC9tD XKiwt7AE9NN6RYHwga/2hbNKLf8Bu7g/YMheitaLQkiGRWXr7Nf20JsCIZ9sT75BSj8/Wz gmPYxso/vcWd9U8ZekFIKejraZ7Lz46J85XNO1ddwX9NfH0byUeeiA3ZErvaHIVeuaxVSI TZfclMhqXqqENmU9KQ0i2A3lZOy2EQ2FmMXHVv2t/RKVweHozxtwuOrSZF5QPFDwIrkUjB Iqa9yrNfPmWeAmmFSCR/Quw/1Z9FxdLezIo5EdJur8cTa3AlAh65QV9zhRU0pw== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1653965646; a=rsa-sha256; cv=none; b=pu0XQI45DZBqe0Gc4XigyC9AZ1oTUCHFqqCNtFbnDQhGmH1RRQpQMxWaS4iUTl6zZplY/q ROBZGEjp9RCNry28+7FOZMgJ1F/80dramCZpLC8yPj/4xDvapK2s7lnNpgd099nv1QE5Ie mQOkONPIk66kEMwJsRI9kTHKYeldUMvGZ1QSJy72fCFwqrAKAi1ar1mDB+b6V8S4PXE6OJ WvUVGiioy2VkH4HdYlEUeVnh7AEvQCuJArC+LUjV6o5lC/hXyKONT2Nevy6fNrLk/7SoVJ 2Cnuwy0X7TdoQK/VHOpSSjxkccOHCH8eeGr1DqMGKdHjPQriSu8NNv0RaI5HEw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=ae57fbc7ec65fcc75575a55c911e0da32ea9c20d commit ae57fbc7ec65fcc75575a55c911e0da32ea9c20d Author: Alexander Motin AuthorDate: 2022-05-31 02:51:00 +0000 Commit: Alexander Motin CommitDate: 2022-05-31 02:54:00 +0000 hwpmc: Update Intel's programmable counters restrictions. Primarily remove unneeded restrictions from later CPUs. MFC after: 1 month --- sys/dev/hwpmc/hwpmc_core.c | 101 ++++++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 47 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index 73cfee0b3975..043ca95a305f 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -613,20 +613,22 @@ iap_event_corei7_ok_on_counter(uint8_t evsel, int ri) uint32_t mask; switch (evsel) { - /* - * Events valid only on counter 0, 1. - */ - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x51: - case 0x63: - mask = 0x3; + /* Events valid only on counter 0, 1. */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x4C: + case 0x4E: + case 0x51: + case 0x52: + case 0x53: + case 0x63: + mask = 0x3; break; - - default: - mask = ~0; /* Any row index is ok. */ + /* Any row index is ok. */ + default: + mask = ~0; } return (mask & (1 << ri)); @@ -638,26 +640,23 @@ iap_event_westmere_ok_on_counter(uint8_t evsel, int ri) uint32_t mask; switch (evsel) { - /* - * Events valid only on counter 0. - */ - case 0x60: - case 0xB3: + /* Events valid only on counter 0. */ + case 0x60: + case 0xB3: mask = 0x1; break; - /* - * Events valid only on counter 0, 1. - */ - case 0x4C: - case 0x4E: - case 0x51: - case 0x63: + /* Events valid only on counter 0, 1. */ + case 0x4C: + case 0x4E: + case 0x51: + case 0x52: + case 0x63: mask = 0x3; break; - + /* Any row index is ok. */ default: - mask = ~0; /* Any row index is ok. */ + mask = ~0; } return (mask & (1 << ri)); @@ -669,34 +668,35 @@ iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri) uint32_t mask; switch (evsel) { - /* Events valid only on counter 0. */ - case 0xB7: + /* Events valid only on counter 0. */ + case 0xB7: mask = 0x1; break; - /* Events valid only on counter 1. */ + /* Events valid only on counter 1. */ case 0xC0: mask = 0x2; break; - /* Events valid only on counter 2. */ + /* Events valid only on counter 2. */ case 0x48: case 0xA2: case 0xA3: mask = 0x4; break; - /* Events valid only on counter 3. */ + /* Events valid only on counter 3. */ case 0xBB: case 0xCD: mask = 0x8; break; + /* Any row index is ok. */ default: - mask = ~0; /* Any row index is ok. */ + mask = ~0; } return (mask & (1 << ri)); } static int -iap_event_ok_on_counter(uint8_t evsel, int ri) +iap_event_core_ok_on_counter(uint8_t evsel, int ri) { uint32_t mask; @@ -748,34 +748,41 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, ev = IAP_EVSEL_GET(iap->pm_iap_config); switch (core_cputype) { + case PMC_CPU_INTEL_CORE: + case PMC_CPU_INTEL_CORE2: + case PMC_CPU_INTEL_CORE2EXTREME: + if (iap_event_core_ok_on_counter(ev, ri) == 0) + return (EINVAL); case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_NEHALEM_EX: if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: + case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_WESTMERE_EX: + if (iap_event_westmere_ok_on_counter(ev, ri) == 0) + return (EINVAL); + break; case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL_XEON: + case PMC_CPU_INTEL_BROADWELL: + case PMC_CPU_INTEL_BROADWELL_XEON: if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) return (EINVAL); break; - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - if (iap_event_westmere_ok_on_counter(ev, ri) == 0) - return (EINVAL); - break; + case PMC_CPU_INTEL_ATOM: + case PMC_CPU_INTEL_ATOM_SILVERMONT: + case PMC_CPU_INTEL_ATOM_GOLDMONT: + case PMC_CPU_INTEL_SKYLAKE: + case PMC_CPU_INTEL_SKYLAKE_XEON: + case PMC_CPU_INTEL_ICELAKE: + case PMC_CPU_INTEL_ICELAKE_XEON: default: - if (iap_event_ok_on_counter(ev, ri) == 0) - return (EINVAL); + break; } pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config;