From nobody Wed Dec 08 08:34:50 2021 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id AE51118DC00D; Wed, 8 Dec 2021 08:34:51 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4J89T71Npzz4cYd; Wed, 8 Dec 2021 08:34:51 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id EA14510587; Wed, 8 Dec 2021 08:34:50 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 1B88YooR097280; Wed, 8 Dec 2021 08:34:50 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 1B88YoFx097279; Wed, 8 Dec 2021 08:34:50 GMT (envelope-from git) Date: Wed, 8 Dec 2021 08:34:50 GMT Message-Id: <202112080834.1B88YoFx097279@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Wojciech Macek Subject: git: 3785106a5bd9 - main - sdhci_fsl_fdt: Implement pulse width detection errata List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: wma X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 3785106a5bd9e3f37f65f8697674114643e40e39 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1638952491; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=GndFmk7EL5lCD56x1IY1eMRwR+XacbZ/NAUC3g4jtU8=; b=HS4Stw96x/Q2P0EATTDMVhdJU0kxy3dXHq7X2lj3gP9slmbLLels1f2+XeNTTA89DD09p/ RlWeHAp5NjqJ3/mqpR8Zk5u+Az7vsdq5bI3rVsW7jAE3dBxevQZmuLuOk7B8e15dzfX+85 aTOlhMF7lVOsb4zlD3OViE/dtt+ufSp2PceJ7yTDhQtVssyr8e1TC0zw46v5NYpcGmnJju HJNLMf+faPUxmcmz6XfLXMEdkgS7G34MqnQ0dGkKaE6s4/BUcmBBXd3ADGXRhYi0UmdaAD J05geaEmuth4D41b4b82ULcqw9dc2NC8qIWFbL56bp0BdAiSWE4ZvAr86AweFg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1638952491; a=rsa-sha256; cv=none; b=Mo39HhyZq6FMmsUFH79/3XjqVXlpNxkc44da85WZUJMihumYxCaDthPf6dd474fa+rdr9J 4oQOSWhMuElptAkwBJ4Aqo0zaj+M0PN8CvZGnIpsv2rx//OibaAZxpAPaawe6RsE09m9a0 sxQas+wxYevljo8mYOw/l5FP0Rshni1DqM5o87+GVd/qbG/1AX27ZbVcmWVLKxJr9Q69uP hNRtLwIp88l3cy2UtqAUijVTgnuTFGzODXdHwHk4fEQiC8CcadKmGAPsjv3f94ABFSBRnH W9dxdFx/tBFgd5+sPNo6ZVWtiCe1wXCS35A9BuMSX8lSnjc1OXSvSfst9YG7wA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by wma: URL: https://cgit.FreeBSD.org/src/commit/?id=3785106a5bd9e3f37f65f8697674114643e40e39 commit 3785106a5bd9e3f37f65f8697674114643e40e39 Author: Hubert Mazur AuthorDate: 2021-12-06 08:18:00 +0000 Commit: Wojciech Macek CommitDate: 2021-12-08 08:34:19 +0000 sdhci_fsl_fdt: Implement pulse width detection errata Some boards do not detect pulse width reliably. Implement workaround by writing 0 to special register. Apply errata for board by adding flag to chosen soc specific data. Obtained from: Semihalf Sponsored by: Alstom Group Reviewed by: mw, manu Differential Revision: https://reviews.freebsd.org/D33222 --- sys/dev/sdhci/sdhci_fsl_fdt.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/sys/dev/sdhci/sdhci_fsl_fdt.c b/sys/dev/sdhci/sdhci_fsl_fdt.c index 06e3afeb4b09..af89cd344b0a 100644 --- a/sys/dev/sdhci/sdhci_fsl_fdt.c +++ b/sys/dev/sdhci/sdhci_fsl_fdt.c @@ -1,8 +1,8 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2020 Alstom Group. - * Copyright (c) 2020 Semihalf. + * Copyright (c) 2020 - 2021 Alstom Group. + * Copyright (c) 2020 - 2021 Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -90,6 +90,9 @@ __FBSDID("$FreeBSD$"); #define SDHCI_FSL_TBCTL 0x120 #define SDHCI_FSL_TBCTL_TBEN (1 << 2) +#define SDHCI_FSL_DLLCFG1 0x164 +#define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31) + #define SDHCI_FSL_ESDHC_CTRL 0x40c #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) @@ -97,6 +100,9 @@ __FBSDID("$FreeBSD$"); #define SDHCI_FSL_CAN_VDD_MASK \ (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330) +/* Some platforms do not detect pulse width correctly. */ +#define SDHCI_FSL_UNRELIABLE_PULSE_DET (1 << 0) + struct sdhci_fsl_fdt_softc { device_t dev; const struct sdhci_fsl_fdt_soc_data *soc_data; @@ -120,12 +126,14 @@ struct sdhci_fsl_fdt_softc { struct sdhci_fsl_fdt_soc_data { int quirks; int baseclk_div; + uint8_t errata; }; static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = { .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, .baseclk_div = 2, + .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET, }; static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { @@ -730,6 +738,16 @@ sdhci_fsl_fdt_attach(device_t dev) sc->slot.max_clk = sc->maxclk_hz; sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); + /* + * Pulse width detection is not reliable on some boards. Perform + * workaround by clearing register's bit according to errata. + */ + if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) { + val = RD4(sc, SDHCI_FSL_DLLCFG1); + val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH; + WR4(sc, SDHCI_FSL_DLLCFG1, val); + } + /* * Set the buffer watermark level to 128 words (512 bytes) for both * read and write. The hardware has a restriction that when the read or