git: e2692e8aa2a9 - stable/14 - bnxt_en: Update HSI header
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Date: Sun, 27 Apr 2025 22:06:09 UTC
The branch stable/14 has been updated by imp:
URL: https://cgit.FreeBSD.org/src/commit/?id=e2692e8aa2a921c0d76af0b8b8757ce95572a140
commit e2692e8aa2a921c0d76af0b8b8757ce95572a140
Author: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
AuthorDate: 2025-04-02 11:26:27 +0000
Commit: Warner Losh <imp@FreeBSD.org>
CommitDate: 2025-04-27 22:02:58 +0000
bnxt_en: Update HSI header
Update HSI header to support Thor2 controllers.
MFC-After: 3 days
Differential-Revision: https://reviews.freebsd.org/D49726
(cherry picked from commit bb90baed6c275495b03adc5569346a59fce2a3c8)
---
sys/dev/bnxt/bnxt_en/bnxt.h | 6 +-
sys/dev/bnxt/bnxt_en/hsi_struct_def.h | 3139 ++++++++++++++++++++++++++-------
2 files changed, 2529 insertions(+), 616 deletions(-)
diff --git a/sys/dev/bnxt/bnxt_en/bnxt.h b/sys/dev/bnxt/bnxt_en/bnxt.h
index 815fe68233c6..20d0fd2c81c0 100644
--- a/sys/dev/bnxt/bnxt_en/bnxt.h
+++ b/sys/dev/bnxt/bnxt_en/bnxt.h
@@ -781,16 +781,16 @@ struct bnxt_ctx_mem_type {
#define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW
#define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW
#define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW
-#define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC
-#define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC
#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
+#define BNXT_CTX_V2_MAX (HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE + 1)
+
struct bnxt_ctx_mem_info {
u8 tqm_fp_rings_count;
u32 flags;
#define BNXT_CTX_FLAG_INITED 0x01
- struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_MAX];
+ struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
};
struct bnxt_hw_resc {
diff --git a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h
index baecfc8f659c..5914c70ce671 100644
--- a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h
+++ b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h
@@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
- * Copyright (c) 2024 Broadcom, All Rights Reserved.
+ * Copyright (c) 2025 Broadcom, All Rights Reserved.
* The term Broadcom refers to Broadcom Limited and/or its subsidiaries
*
* Redistribution and use in source and binary forms, with or without
@@ -31,7 +31,7 @@
__FBSDID("$FreeBSD$");
/*
- * Copyright(c) 2001-2024, Broadcom. All rights reserved. The
+ * Copyright(c) 2001-2025, Broadcom. All rights reserved. The
* term Broadcom refers to Broadcom Inc. and/or its subsidiaries.
* Proprietary and Confidential Information.
*
@@ -80,7 +80,7 @@ typedef struct hwrm_cmd_hdr {
* physical address (HPA) or a guest physical address (GPA) and must
* point to a physically contiguous block of memory.
*/
- uint64_t resp_addr;
+ uint64_t resp_addr;
} hwrm_cmd_hdr_t, *phwrm_cmd_hdr_t;
/* This is the HWRM response header. */
@@ -596,7 +596,10 @@ typedef struct hwrm_short_input {
((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \
((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \
((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \
- "Unknown decode" )))))))))))))))))))))))))))))))))))) : \
+ ((x) == 0x1c2 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_ADD": \
+ ((x) == 0x1c3 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE": \
+ ((x) == 0x1c4 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY": \
+ "Unknown decode" ))))))))))))))))))))))))))))))))))))))) : \
(((x) < 0x280) ? \
((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \
((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \
@@ -625,6 +628,8 @@ typedef struct hwrm_short_input {
((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \
((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \
((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \
+ ((x) == 0x230 ? "HWRM_PORT_POE_CFG": \
+ ((x) == 0x231 ? "HWRM_PORT_POE_QCFG": \
((x) == 0x258 ? "HWRM_UDCC_QCAPS": \
((x) == 0x259 ? "HWRM_UDCC_CFG": \
((x) == 0x25a ? "HWRM_UDCC_QCFG": \
@@ -634,7 +639,10 @@ typedef struct hwrm_short_input {
((x) == 0x25e ? "HWRM_UDCC_COMP_CFG": \
((x) == 0x25f ? "HWRM_UDCC_COMP_QCFG": \
((x) == 0x260 ? "HWRM_UDCC_COMP_QUERY": \
- "Unknown decode" )))))))))))))))))))))))))))))))))))) : \
+ ((x) == 0x261 ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \
+ ((x) == 0x262 ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \
+ ((x) == 0x263 ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \
+ "Unknown decode" ))))))))))))))))))))))))))))))))))))))))) : \
(((x) < 0x300) ? \
((x) == 0x2bc ? "HWRM_TF": \
((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \
@@ -701,14 +709,12 @@ typedef struct hwrm_short_input {
((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \
((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \
((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \
- ((x) == 0x39c ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \
- ((x) == 0x39d ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \
- ((x) == 0x39e ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \
- "Unknown decode" ))))))))))))))))))))))))))))))) : \
+ "Unknown decode" )))))))))))))))))))))))))))) : \
(((x) < 0x480) ? \
((x) == 0x400 ? "HWRM_SV": \
"Unknown decode" ) : \
(((x) < 0xff80) ? \
+ ((x) == 0xff0e ? "HWRM_DBG_SERDES_TEST": \
((x) == 0xff0f ? "HWRM_DBG_LOG_BUFFER_FLUSH": \
((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
@@ -738,8 +744,11 @@ typedef struct hwrm_short_input {
((x) == 0xff29 ? "HWRM_DBG_USEQ_RUN": \
((x) == 0xff2a ? "HWRM_DBG_USEQ_DELIVERY_REQ": \
((x) == 0xff2b ? "HWRM_DBG_USEQ_RESP_HDR": \
- "Unknown decode" ))))))))))))))))))))))))))))) : \
- (((x) <= 0xffff) ? \
+ ((x) == 0xff2c ? "HWRM_DBG_COREDUMP_CAPTURE": \
+ ((x) == 0xff2d ? "HWRM_DBG_PTRACE": \
+ ((x) == 0xff2e ? "HWRM_DBG_SIM_CABLE_STATE": \
+ "Unknown decode" ))))))))))))))))))))))))))))))))) : \
+ (((x) <= UINT16_MAX) ? \
((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \
((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \
((x) == 0xffec ? "HWRM_NVM_DEFRAG": \
@@ -1248,13 +1257,25 @@ typedef struct cmd_nums {
#define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2)
/* The command is used to query a link aggr group. */
#define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3)
+ /* This command is use to add TimeTX packet pacing rate. */
+ #define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD UINT32_C(0x1c2)
+ /*
+ * This command is use to delete TimeTX packet pacing rate
+ * from the rate table.
+ */
+ #define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE UINT32_C(0x1c3)
+ /*
+ * This command is used to retrieve all the TimeTX pacing rates
+ * from the rate table that have been added for the function.
+ */
+ #define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY UINT32_C(0x1c4)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
#define HWRM_SELFTEST_EXEC UINT32_C(0x201)
/* Experimental */
#define HWRM_SELFTEST_IRQ UINT32_C(0x202)
- /* Experimental */
+ /* Experimental (deprecated) */
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
@@ -1326,6 +1347,16 @@ typedef struct cmd_nums {
#define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219)
/* Query the statistics for doorbell drops due to various error conditions. */
#define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a)
+ /*
+ * The command is used to enable/disable the power on ethernet for
+ * a particular I/O expander port.
+ */
+ #define HWRM_PORT_POE_CFG UINT32_C(0x230)
+ /*
+ * The command is used to query whether the power on ethernet
+ * is enabled/disabled for a particular I/O expander port.
+ */
+ #define HWRM_PORT_POE_QCFG UINT32_C(0x231)
/*
* This command returns the capabilities related to User Defined
* Congestion Control on a function.
@@ -1350,6 +1381,18 @@ typedef struct cmd_nums {
#define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f)
/* This command queries the status and statistics of the computation unit. */
#define HWRM_UDCC_COMP_QUERY UINT32_C(0x260)
+ /*
+ * This command is used to query the pfc watchdog max configurable
+ * timeout value.
+ */
+ #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x261)
+ /* This command is used to set the PFC watchdog timeout value. */
+ #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x262)
+ /*
+ * This command is used to query the current configured pfc watchdog
+ * timeout value.
+ */
+ #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x263)
/* Experimental */
#define HWRM_TF UINT32_C(0x2bc)
/* Experimental */
@@ -1472,20 +1515,10 @@ typedef struct cmd_nums {
#define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a)
/* TruFlow command to query the resource usage state. */
#define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b)
- /*
- * This command is used to query the pfc watchdog max configurable
- * timeout value.
- */
- #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x39c)
- /* This command is used to set the PFC watchdog timeout value. */
- #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x39d)
- /*
- * This command is used to query the current configured pfc watchdog
- * timeout value.
- */
- #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x39e)
/* Experimental */
#define HWRM_SV UINT32_C(0x400)
+ /* Run a PCIe or Ethernet serdes test and retrieve test data. */
+ #define HWRM_DBG_SERDES_TEST UINT32_C(0xff0e)
/* Flush any trace buffer data that has not been sent to the host. */
#define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f)
/* Experimental */
@@ -1543,6 +1576,18 @@ typedef struct cmd_nums {
#define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
/* Experimental */
#define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
+ /*
+ * This command is used to request the firmware to store a coredump
+ * into Host memory previously specified with the
+ * HWRM_DBG_CRASHDUMP_MEDIUM_CFG API
+ */
+ #define HWRM_DBG_COREDUMP_CAPTURE UINT32_C(0xff2c)
+ #define HWRM_DBG_PTRACE UINT32_C(0xff2d)
+ /*
+ * This command is used to request the firmware to simulate cable insert
+ * or removal.
+ */
+ #define HWRM_DBG_SIM_CABLE_STATE UINT32_C(0xff2e)
#define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea)
#define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb)
#define HWRM_NVM_DEFRAG UINT32_C(0xffec)
@@ -1719,7 +1764,7 @@ typedef struct ret_codes {
(((x) < 0x8080) ? \
((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \
"Unknown decode" ) : \
- (((x) <= 0xffff) ? \
+ (((x) <= UINT16_MAX) ? \
((x) == 0xfffe ? "UNKNOWN_ERR": \
((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
"Unknown decode" )) : \
@@ -1803,8 +1848,8 @@ typedef struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 3
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 42
-#define HWRM_VERSION_STR "1.10.3.42"
+#define HWRM_VERSION_RSVD 61
+#define HWRM_VERSION_STR "1.10.3.61"
/****************
* hwrm_ver_get *
@@ -3299,8 +3344,7 @@ typedef struct tx_bd_short {
*
* This value must be valid on all BDs of a packet.
*/
- uint32_t addr_lo;
- uint32_t addr_hi;
+ uint64_t addr;
} tx_bd_short_t, *ptx_bd_short_t;
/* tx_bd_long (size:128b/16B) */
@@ -3801,8 +3845,7 @@ typedef struct tx_bd_long_inline {
* This field must be valid on the first BD of a packet.
*/
uint32_t opaque;
- uint32_t unused1_lo;
- uint32_t unused1_hi;
+ uint64_t unused1;
/*
* All bits in this field must be valid on the first BD of a packet.
* Their value on other BDs of the packet is ignored.
@@ -4079,8 +4122,7 @@ typedef struct tx_bd_mp_cmd {
* Tx mid-path command.
*/
uint32_t opaque;
- uint32_t unused1_lo;
- uint32_t unused1_hi;
+ uint64_t unused1;
} tx_bd_mp_cmd_t, *ptx_bd_mp_cmd_t;
/* tx_bd_presync_cmd (size:128b/16B) */
@@ -4226,8 +4268,7 @@ typedef struct tx_bd_timedtx {
* corresponding packet using SO_TXTIME mode of timed transmit.
* This field is applicable only if flags.kind is so_txtime.
*/
- uint32_t tx_time_lo;
- uint32_t tx_time_hi;
+ uint64_t tx_time;
} tx_bd_timedtx_t, *ptx_bd_timedtx_t;
/* rx_prod_pkt_bd (size:128b/16B) */
@@ -4344,8 +4385,7 @@ typedef struct rx_prod_bfr_bd {
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provide start on a host cache line.
*/
- uint32_t addr_lo;
- uint32_t addr_hi;
+ uint64_t addr;
} rx_prod_bfr_bd_t, *prx_prod_bfr_bd_t;
/* rx_prod_agg_bd (size:128b/16B) */
@@ -4397,8 +4437,7 @@ typedef struct rx_prod_agg_bd {
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provide start on a host cache line.
*/
- uint32_t addr_lo;
- uint32_t addr_hi;
+ uint64_t addr;
} rx_prod_agg_bd_t, *prx_prod_agg_bd_t;
/* cfa_cmpls_cmp_data_msg (size:128b/16B) */
@@ -9791,8 +9830,28 @@ typedef struct hwrm_async_event_cmpl {
* how much of its host buffer has been populated by the firmware.
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c)
+ /*
+ * Memory mapping between GPA and HPA has been configured for
+ * a peer device. Inform driver to pick up the new mapping.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE UINT32_C(0x4d)
+ /*
+ * Used to notify representor endpoint in the driver about pair creation
+ * in the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE UINT32_C(0x4e)
+ /*
+ * VF statistics context change. Informs PF driver that a VF
+ * statistics context has either been allocated or freed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE UINT32_C(0x4f)
+ /*
+ * coredump collection into host DMA address. Informs PF driver that
+ * the coredump has been captured.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP UINT32_C(0x50)
/* Maximum Registrable event id. */
- #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x4d)
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x51)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -9869,8 +9928,12 @@ typedef struct hwrm_async_event_cmpl {
((x) == 0x4a ? "CTX_ERROR": \
((x) == 0x4b ? "UDCC_SESSION_CHANGE": \
((x) == 0x4c ? "DBG_BUF_PRODUCER": \
- ((x) == 0x4d ? "MAX_RGTR_EVENT_ID": \
- "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))) : \
+ ((x) == 0x4d ? "PEER_MMAP_CHANGE": \
+ ((x) == 0x4e ? "REPRESENTOR_PAIR_CHANGE": \
+ ((x) == 0x4f ? "VF_STAT_CHANGE": \
+ ((x) == 0x50 ? "HOST_COREDUMP": \
+ ((x) == 0x51 ? "MAX_RGTR_EVENT_ID": \
+ "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))) : \
(((x) < 0x100) ? \
((x) == 0xfe ? "FW_TRACE_MSG": \
((x) == 0xff ? "HWRM_ERROR": \
@@ -10307,6 +10370,30 @@ typedef struct hwrm_async_event_cmpl_port_phy_cfg_change {
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
/* Event specific data */
uint32_t event_data2;
+ /*
+ * This value indicates the current status of the optics module on
+ * this port. the same information can be found in the module_status
+ * field of the HWRM_PORT_PHY_QCFG response
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_MASK UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_SFT 0
+ /* Module is inserted and accepted */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NONE UINT32_C(0x0)
+ /* Module is rejected and transmit side Laser is disabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_DISABLETX UINT32_C(0x1)
+ /* Module mismatch warning. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_MISMATCH UINT32_C(0x2)
+ /* Module is rejected and powered down. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_PWRDOWN UINT32_C(0x3)
+ /* Module is not inserted. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTINSERTED UINT32_C(0x4)
+ /* Module is powered down because of over current fault. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_CURRENTFAULT UINT32_C(0x5)
+ /* Module is overheated. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_OVERHEATED UINT32_C(0x6)
+ /* Module status is not applicable. */
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_LAST HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTAPPLICABLE
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
@@ -12244,6 +12331,72 @@ typedef struct hwrm_async_event_udcc_session_change {
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT 0
} hwrm_async_event_udcc_session_change_t, *phwrm_async_event_udcc_session_change_t;
+/* hwrm_async_event_representor_pair_change (size:128b/16B) */
+
+typedef struct hwrm_async_event_representor_pair_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_MASK UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_LAST HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform the driver
+ * that firmware has modified a representor pair.
+ */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_ID_REPRESENTOR_PAIR_CHANGE UINT32_C(0x4e)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_ID_LAST HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_ID_REPRESENTOR_PAIR_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Representor pair operation code */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_MASK UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_SFT 0
+ /* pair has been created */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_CREATED UINT32_C(0x0)
+ /* pair has been deleted */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_DELETED UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_LAST HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_DELETED
+ /* DSCP insert operation code */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_MASK UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_SFT 8
+ /* allow dscp modification */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_MODIFY (UINT32_C(0x0) << 8)
+ /* skip dscp modification */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_IGNORE (UINT32_C(0x1) << 8)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_LAST HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_IGNORE
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Representor endpoint fid which was modified */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_EP_FID_MASK UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_EP_FID_SFT 0
+ /* Representor uplink fid which was modified */
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_REP_FID_MASK UINT32_C(0xffff0000)
+ #define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_REP_FID_SFT 16
+} hwrm_async_event_representor_pair_change_t, *phwrm_async_event_representor_pair_change_t;
+
/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */
typedef struct hwrm_async_event_cmpl_dbg_buf_producer {
@@ -12314,9 +12467,62 @@ typedef struct hwrm_async_event_cmpl_dbg_buf_producer {
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE UINT32_C(0x5)
/* RoCE HWRM trace. */
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6)
- #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE
+ /* Context Accelerator CPU 0 trace. */
+ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE UINT32_C(0x7)
+ /* Context Accelerator CPU 1 trace. */
+ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE UINT32_C(0x8)
+ /* Context Accelerator CPU 2 trace. */
+ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE UINT32_C(0x9)
+ /* RIGP1 trace. */
+ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE UINT32_C(0xa)
+ #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE
} hwrm_async_event_cmpl_dbg_buf_producer_t, *phwrm_async_event_cmpl_dbg_buf_producer_t;
+/* hwrm_async_event_cmpl_peer_mmap_change (size:128b/16B) */
+
+typedef struct hwrm_async_event_cmpl_peer_mmap_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_MASK UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform the driver
+ * that the memory mapping for a peer device is set. The driver
+ * will need to query using get_structured_data.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_EVENT_ID_PEER_MMAP_CHANGE UINT32_C(0x4d)
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_EVENT_ID_PEER_MMAP_CHANGE
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} hwrm_async_event_cmpl_peer_mmap_change_t, *phwrm_async_event_cmpl_peer_mmap_change_t;
+
/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
typedef struct hwrm_async_event_cmpl_fw_trace_msg {
@@ -12948,6 +13154,114 @@ typedef struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported {
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED
} hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t, *phwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t;
+/* hwrm_async_event_cmpl_vf_stat_change (size:128b/16B) */
+
+typedef struct hwrm_async_event_cmpl_vf_stat_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_MASK UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * VF statistics context change. Informs PF driver that a VF
+ * statistics context has either been allocated or freed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_ID_VF_STAT_CHANGE UINT32_C(0x4f)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_ID_VF_STAT_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ /*
+ * VF ID that allocated the stats context. This is zero-based and
+ * relative to each PF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_VF_ID_MASK UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_VF_ID_SFT 0
+ /*
+ * A value of zero signals to the PF driver that it can free the host
+ * buffer associated with the statistics context.
+ * A non-zero values signals to the PF driver that it should allocate
+ * a host buffer for the statistics context and inform the firmware
+ * via HWRM_STAT_CTX_ALLOC. The PF driver must provide the sequence id
+ * in the corresponding HWRM_STAT_CTX_ALLOC request so that firmware
+ * can correlate it to the VF statistics context.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_ACTION_SEQUENCE_ID_MASK UINT32_C(0xffff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_ACTION_SEQUENCE_ID_SFT 16
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* VF statistics context identifier */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA1_STAT_CTX_ID_MASK UINT32_C(0xffffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA1_STAT_CTX_ID_SFT 0
+} hwrm_async_event_cmpl_vf_stat_change_t, *phwrm_async_event_cmpl_vf_stat_change_t;
+
+/* hwrm_async_event_cmpl_host_coredump (size:128b/16B) */
+
+typedef struct hwrm_async_event_cmpl_host_coredump {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_MASK UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * coredump collection into host DMA address. Informs PF driver that
+ * the coredump has been captured.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_EVENT_ID_HOST_COREDUMP UINT32_C(0x50)
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_EVENT_ID_HOST_COREDUMP
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} hwrm_async_event_cmpl_host_coredump_t, *phwrm_async_event_cmpl_host_coredump_t;
+
/* metadata_base_msg (size:64b/8B) */
typedef struct metadata_base_msg {
@@ -14491,7 +14805,7 @@ typedef struct hwrm_func_qcaps_input {
uint8_t unused_0[6];
} hwrm_func_qcaps_input_t, *phwrm_func_qcaps_input_t;
-/* hwrm_func_qcaps_output (size:1088b/136B) */
+/* hwrm_func_qcaps_output (size:1152b/144B) */
typedef struct hwrm_func_qcaps_output {
/* The specific error status for the command. */
@@ -15210,6 +15524,43 @@ typedef struct hwrm_func_qcaps_output {
* query and clear of the port loopback statistics.
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED UINT32_C(0x2000000)
+ /*
+ * When this bit is '1', it indicates that the device supports
+ * migrating egress NIC flows to Truflow.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED UINT32_C(0x4000000)
+ /*
+ * When this bit is '1', it indicates that the device supports
+ * multiple lossless CoS queues.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED UINT32_C(0x8000000)
+ /*
+ * When this bit is '1', it indicates that the firmware supports
+ * peer memory map storing feature.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_PEER_MMAP_SUPPORTED UINT32_C(0x10000000)
+ /*
+ * When this bit is '1', it indicates that the device supports Timed
+ * Transmit packet pacing; this is applicable to L2 flows only.
+ * Host software passes the transmit rate of an L2 flow to the
+ * hardware and hardware uses this rate to derive the transmit time
+ * for scheduling packet transmission of the flow.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED UINT32_C(0x20000000)
+ /*
+ * When this bit is '1', it indicates that the device supports VF
+ * statistics ejection. Firmware is capable of copying VF statistics
+ * to two host buffers - one buffer allocated by VF driver and
+ * another buffer allocated by the parent PF driver. This bit is
+ * only set on a PF.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED UINT32_C(0x40000000)
+ /*
+ * When this bit is '1', it indicates that the parent PF allocated
+ * the Host DMA buffer to capture the coredump. So that any VF
+ * driver instance can issue HWRM_DBG_COREDUMP_CAPTURE command
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED UINT32_C(0x80000000)
uint16_t tunnel_disable_flag;
/*
* When this bit is '1', it indicates that the VXLAN parsing
@@ -15277,7 +15628,15 @@ typedef struct hwrm_func_qcaps_output {
* the number contexts per partition.
*/
uint16_t ctxs_per_partition;
- uint8_t unused_2[2];
+ /*
+ * The maximum number of tso segments that NIC can handle during the
+ * large segmentation offload.
+ * If this field is zero, that means there is no limit on the TSO
+ * segment limit.
+ * Note that this field will be zero for older firmware that
+ * doesn't report the max TSO segment limit.
+ */
+ uint16_t max_tso_segs;
/*
* The maximum number of address vectors that may be allocated across
* all VFs for the function. This is valid only on the PF with VF RoCE
@@ -15320,7 +15679,16 @@ typedef struct hwrm_func_qcaps_output {
* (SR-IOV) disabled or on a VF.
*/
uint32_t roce_vf_max_gid;
- uint8_t unused_3[3];
+ uint32_t flags_ext3;
+ /*
+ * When this bit is '1', firmware supports the driver using
+ * FUNC_CFG (or FUNC_VF_CFG) to decrease resource reservations
+ * while some resources are still allocated. An error is returned
+ * if the driver tries to set the reservation to be less than the
+ * number of allocated resources.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP UINT32_C(0x1)
+ uint8_t unused_3[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -15941,7 +16309,12 @@ typedef struct hwrm_func_qcfg_output {
* value is used if ring MTU is not specified.
*/
uint16_t host_mtu;
- uint8_t unused_3[2];
+ uint16_t flags2;
+ /*
+ * If set to 1, then VF drivers are requested to insert a DSCP
+ * value into all outgoing L2 packets such that DSCP=VF ID modulo 64
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS2_SRIOV_DSCP_INSERT_ENABLED UINT32_C(0x1)
uint8_t unused_4[2];
/*
* KDNet mode for the port for this function. If a VF, KDNet
@@ -17631,6 +18004,14 @@ typedef struct hwrm_func_drv_rgtr_input {
* function.
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE UINT32_C(0x800)
+ /*
+ * When this bit is 1, the function's driver is indicating to the
+ * firmware that the Egress NIC flows will be programmed by the
+ * TruFlow application and the firmware flow manager should reject
+ * flow-create commands that programs Egress lookup flows for this
+ * function.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_EGRESS_NIC_FLOW_MODE UINT32_C(0x1000)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -22100,14 +22481,14 @@ typedef struct hwrm_func_ptp_ext_qcfg_output {
uint8_t valid;
} hwrm_func_ptp_ext_qcfg_output_t, *phwrm_func_ptp_ext_qcfg_output_t;
-/***************************
- * hwrm_func_key_ctx_alloc *
- ***************************/
+/*************************************
+ * hwrm_func_timedtx_pacing_rate_add *
+ *************************************/
-/* hwrm_func_key_ctx_alloc_input (size:384b/48B) */
+/* hwrm_func_timedtx_pacing_rate_add_input (size:192b/24B) */
-typedef struct hwrm_func_key_ctx_alloc_input {
+typedef struct hwrm_func_timedtx_pacing_rate_add_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -22136,61 +22517,20 @@ typedef struct hwrm_func_key_ctx_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Function ID. */
- uint16_t fid;
/*
- * Number of Key Contexts to be allocated.
- * When running in the XID partition mode, if the call is made by
- * a VF driver, this field specifies the number of XIDs requested
- * by the VF driver. The XID partitions are managed by the PF
- * driver in XID partition mode and the VF command will be
- * redirected to the PF driver. The PF driver may reduce this
- * number if it cannot allocate a big enough block of XID
- * partitions to satisfy the request.
- * This field must not exceed the maximum batch size specified in
- * the max_key_ctxs_alloc field of the HWRM_FUNC_QCAPS response,
- * must not be zero, and must be integer multiples of the
- * partition size specified in the ctxs_per_partition field of
- * the HWRM_FUNC_QCAPS response.
- */
- uint16_t num_key_ctxs;
- /*
- * DMA buffer size in bytes. This field in invalid in the XID
- * partition mode.
- */
- uint32_t dma_bufr_size_bytes;
- /* Key Context type. */
- uint8_t key_ctx_type;
- /* KTLS Tx Key Context type. */
- #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
- /* KTLS Rx Key Context type. */
- #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
- /* QUIC Tx Key Context type. */
- #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
- /* QUIC Rx Key Context type. */
- #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
- #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX
- uint8_t unused_0[7];
- /*
- * Host DMA address to send back KTLS context IDs. This field is
- * invalid in the XID partition mode.
- */
- uint64_t host_dma_addr;
- /*
- * This field is only used by the PF driver that manages the XID
- * partitions. This field specifies the starting XID of one or
- * more contiguous XID partitions allocated by the PF driver.
- * This field is not used by the VF driver.
- * If the call is successful, this starting XID value will be
- * returned in the partition_start_xid field of the response.
+ * This field indicates TimedTx pacing rate in kbps.
+ * The driver needs to add the rate into the hardware rate table
+ * before requesting the pacing rate for a flow in TimedTX BD and
+ * this addition should be done for each function rather than for
+ * each flow/QP within the function.
*/
- uint32_t partition_start_xid;
- uint8_t unused_1[4];
-} hwrm_func_key_ctx_alloc_input_t, *phwrm_func_key_ctx_alloc_input_t;
+ uint32_t rate;
+ uint8_t unused_0[4];
+} hwrm_func_timedtx_pacing_rate_add_input_t, *phwrm_func_timedtx_pacing_rate_add_input_t;
-/* hwrm_func_key_ctx_alloc_output (size:192b/24B) */
+/* hwrm_func_timedtx_pacing_rate_add_output (size:128b/16B) */
-typedef struct hwrm_func_key_ctx_alloc_output {
+typedef struct hwrm_func_timedtx_pacing_rate_add_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -22199,26 +22539,13 @@ typedef struct hwrm_func_key_ctx_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Number of Key Contexts that have been allocated. */
- uint16_t num_key_ctxs_allocated;
- /* Control flags. */
- uint8_t flags;
/*
- * When set, it indicates that all key contexts allocated by this
- * command are contiguous. As a result, the driver has to read the
- * start context ID from the first entry of the DMA data buffer
- * and figures out the end context ID by 'start context ID +
- * num_key_ctxs_allocated - 1'. In XID partition mode,
- * this bit should always be set.
+ * This field indicates the logical rate ID that is assigned to the
+ * rate in the rate table. The driver should use this ID for future
+ * reference to this rate.
*/
- #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS UINT32_C(0x1)
- uint8_t unused_0;
- /*
- * This field is only valid in the XID partition mode. It indicates
- * the starting XID that has been allocated.
- */
- uint32_t partition_start_xid;
- uint8_t unused_1[7];
+ uint16_t rate_id;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -22227,16 +22554,279 @@ typedef struct hwrm_func_key_ctx_alloc_output {
* the order of writes has to be such that this field is written last.
*/
uint8_t valid;
-} hwrm_func_key_ctx_alloc_output_t, *phwrm_func_key_ctx_alloc_output_t;
+} hwrm_func_timedtx_pacing_rate_add_output_t, *phwrm_func_timedtx_pacing_rate_add_output_t;
-/**************************
- * hwrm_func_key_ctx_free *
- **************************/
+/****************************************
+ * hwrm_func_timedtx_pacing_rate_delete *
+ ****************************************/
-/* hwrm_func_key_ctx_free_input (size:256b/32B) */
+/* hwrm_func_timedtx_pacing_rate_delete_input (size:192b/24B) */
-typedef struct hwrm_func_key_ctx_free_input {
+typedef struct hwrm_func_timedtx_pacing_rate_delete_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The logical rate ID that is returned in the TimedTX pacing rate
+ * add operation.
+ */
+ uint16_t rate_id;
+ uint8_t unused_0[6];
+} hwrm_func_timedtx_pacing_rate_delete_input_t, *phwrm_func_timedtx_pacing_rate_delete_input_t;
+
+/* hwrm_func_timedtx_pacing_rate_delete_output (size:128b/16B) */
+
+typedef struct hwrm_func_timedtx_pacing_rate_delete_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} hwrm_func_timedtx_pacing_rate_delete_output_t, *phwrm_func_timedtx_pacing_rate_delete_output_t;
+
+/***************************************
+ * hwrm_func_timedtx_pacing_rate_query *
+ ***************************************/
+
+
+/* hwrm_func_timedtx_pacing_rate_query_input (size:192b/24B) */
+
+typedef struct hwrm_func_timedtx_pacing_rate_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
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