From nobody Thu Jan 18 23:39:23 2024 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4TGK300NJsz57Hr0; Thu, 18 Jan 2024 23:39:24 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4TGK2z4ffjz4SMP; Thu, 18 Jan 2024 23:39:23 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1705621163; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=NWiED+ghZZWcD6BKNQxqu8miMYzzzn/fV1R4zHWcrZM=; b=aNxFI2Ithx5qtMRbtWZ6i4ils9CPvACA0P7hT+cDStNY3KpJgwOEWk45TAQlpv5nVheoD5 zZfBa+C0okmQ98TZyOhLMsSUfMojr0ksWcK5uyuiZxDVNGegejHhc8tXo4jXuh+jq7YVEO lPzypKSqWb9SgpwzSwkTIO3OfjYv0n+JOzMDa+4cUU2N1lrCe1BoX8b4TrfRroXvRe7KYl 7lD7AhgPeAOyAXDZt+w3LOkZqf+6sxEBCEp3nWgEpaunCBeTW4QXRlXDhw18lTWQxZsIOx F18Ezwb60xwi6mx754J/l3s1Fmczhb+uhq9eYnunUkSkDuhbfsZcAI4A1CREWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1705621163; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=NWiED+ghZZWcD6BKNQxqu8miMYzzzn/fV1R4zHWcrZM=; b=CRr8D9zCBEoBrZ3bDwpcG/lQuYkdKkYXpu+5P1Y46jRvsM6rzdVr9qOjkyuWWSgPUhCSao uafQ/KOtUtBdaxgnQkay7kjE3X6qFvvbBz3Sxsz2ias6oWfyxhezOPIyWJ04iKpYqFhIVt 4DmAijSKabq680VPdAiTR2PVORfb1aPZFQudACl5Kf8epB32eKpyHS3S43sqKGqOIJfGQP qDi1FR4C4bYua6jo6Oe82Gia9VncfeAKsuMNdqKavx5Oxw/LacYO7eokM2RUZkZrIC6tUA 2XUgd4BZqDRUb9WVXuZ2ztL8HrnuclhtCLGxpwNJEnW1Wkd/coNwbB0tHs5VPQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1705621163; a=rsa-sha256; cv=none; b=cAygfmVPAK7WkvVG/xN7NXozHcY0TtTVI3W49M/P/gO8LfqM18CS+/9XraLZRKS5cNgSri VrKcmWSmBJrdQsMXv7Z7TSP7Dv+xGX+opCPNwWYWCE5d9mYjueTfWJDOaRvkrhf4/cZGv2 JjStPdrVqOxdcLFhUm+fHU/22toBVFtJHZKys9fwUd4GuWtVyTJtB8mnSGqhP4To1VJfze sPXNJiCiFgg9GguWFWovdlLUIqb6LwGPqIxrdO0Z7/Jpj/AtTzzCpRv/qzWrRQHjBr66a9 36NMopmzi/ipnhN7jpo0sNRON5a8ojQND/TI5AenZuKGxz/zhpXRi0G9s0cZPA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4TGK2z3l2kzSMV; Thu, 18 Jan 2024 23:39:23 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 40INdNKH011809; Thu, 18 Jan 2024 23:39:23 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 40INdN4R011806; Thu, 18 Jan 2024 23:39:23 GMT (envelope-from git) Date: Thu, 18 Jan 2024 23:39:23 GMT Message-Id: <202401182339.40INdN4R011806@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: John Baldwin Subject: git: ac64ca647dfc - stable/13 - x86: Refactor pcie_cfgregopen List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jhb X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: ac64ca647dfce284bba09104c65d5aff35be0ce5 Auto-Submitted: auto-generated The branch stable/13 has been updated by jhb: URL: https://cgit.FreeBSD.org/src/commit/?id=ac64ca647dfce284bba09104c65d5aff35be0ce5 commit ac64ca647dfce284bba09104c65d5aff35be0ce5 Author: John Baldwin AuthorDate: 2023-11-29 18:32:16 +0000 Commit: John Baldwin CommitDate: 2024-01-18 23:27:25 +0000 x86: Refactor pcie_cfgregopen Split out some bits of pcie_cfgregopen that only need to be executed once into helper functions in preparation for supporting multiple MCFG entries. Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D42829 (cherry picked from commit 9893a4fd31fa4b2e19a7b9cf786f49b9de50b407) --- sys/amd64/pci/pci_cfgreg.c | 43 +++++++++++++++----------- sys/i386/pci/pci_cfgreg.c | 75 ++++++++++++++++++++++++++++------------------ 2 files changed, 71 insertions(+), 47 deletions(-) diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index 6b95c6fae0ab..dd177b6e9a8c 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -218,28 +218,12 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) mtx_unlock_spin(&pcicfg_mtx); } -int -pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) +static void +pcie_init_badslots(void) { uint32_t val1, val2; int slot; - if (!mcfg_enable) - return (0); - - if (minbus != 0) - return (0); - - if (bootverbose) - printf("PCIe: Memory Mapped configuration base @ 0x%lx\n", - base); - - /* XXX: We should make sure this really fits into the direct map. */ - pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20); - pcie_minbus = minbus; - pcie_maxbus = maxbus; - cfgmech = CFGMECH_PCIE; - /* * On some AMD systems, some of the devices on bus 0 are * inaccessible using memory-mapped PCI config access. Walk @@ -257,6 +241,29 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) pcie_badslots |= (1 << slot); } } +} + +int +pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) +{ + + if (!mcfg_enable) + return (0); + + if (minbus != 0) + return (0); + + if (bootverbose) + printf("PCIe: Memory Mapped configuration base @ 0x%lx\n", + base); + + /* XXX: We should make sure this really fits into the direct map. */ + pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20); + pcie_minbus = minbus; + pcie_maxbus = maxbus; + cfgmech = CFGMECH_PCIE; + + pcie_init_badslots(); return (1); } diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c index ef712fe49fe3..2129782063d3 100644 --- a/sys/i386/pci/pci_cfgreg.c +++ b/sys/i386/pci/pci_cfgreg.c @@ -437,8 +437,8 @@ pcireg_cfgopen(void) return (cfgmech); } -int -pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) +static bool +pcie_init_cache(void) { struct pcie_cfg_list *pcielist; struct pcie_cfg_elem *pcie_array, *elem; @@ -446,26 +446,7 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) struct pcpu *pc; #endif vm_offset_t va; - uint32_t val1, val2; - int i, slot; - - if (!mcfg_enable) - return (0); - - if (minbus != 0) - return (0); - - if (!pae_mode && base >= 0x100000000) { - if (bootverbose) - printf( - "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n", - (uintmax_t)base); - return (0); - } - - if (bootverbose) - printf("PCIe: Memory Mapped configuration base @ 0x%jx\n", - (uintmax_t)base); + int i; #ifdef SMP STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) @@ -474,12 +455,12 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE, M_DEVBUF, M_NOWAIT); if (pcie_array == NULL) - return (0); + return (false); va = kva_alloc(PCIE_CACHE * PAGE_SIZE); if (va == 0) { free(pcie_array, M_DEVBUF); - return (0); + return (false); } #ifdef SMP @@ -495,12 +476,14 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) TAILQ_INSERT_HEAD(pcielist, elem, elem); } } + return (true); +} - pcie_base = base; - pcie_minbus = minbus; - pcie_maxbus = maxbus; - cfgmech = CFGMECH_PCIE; - devmax = 32; +static void +pcie_init_badslots(void) +{ + uint32_t val1, val2; + int slot; /* * On some AMD systems, some of the devices on bus 0 are @@ -519,6 +502,40 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) pcie_badslots |= (1 << slot); } } +} + +int +pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) +{ + + if (!mcfg_enable) + return (0); + + if (minbus != 0) + return (0); + + if (!pae_mode && base >= 0x100000000) { + if (bootverbose) + printf( + "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n", + (uintmax_t)base); + return (0); + } + + if (bootverbose) + printf("PCIe: Memory Mapped configuration base @ 0x%jx\n", + (uintmax_t)base); + + if (!pcie_init_cache()) + return (0); + + pcie_base = base; + pcie_minbus = minbus; + pcie_maxbus = maxbus; + cfgmech = CFGMECH_PCIE; + devmax = 32; + + pcie_init_badslots(); return (1); }