git: 3ef0220e2d0b - stable/13 - arm64: Update the ID_AA64PFR0_EL1 fields

The branch stable/13 has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=3ef0220e2d0b6b0bbfa175c01294a7ab60bbf5c8

commit 3ef0220e2d0b6b0bbfa175c01294a7ab60bbf5c8
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-07-06 14:02:35 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-09-25 10:49:32 +0000

    arm64: Update the ID_AA64PFR0_EL1 fields
    
    While here move to decimal for the _op and _CR definitions to be used
    by a future macro to define the register when the assembler doesn't
    know about it.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D40895
    
    (cherry picked from commit 0766dde9b5587d04c634eda1ab4666203d32a271)
---
 sys/arm64/arm64/identcpu.c | 10 +++++++++-
 sys/arm64/include/armreg.h | 17 ++++++++++++-----
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
index 06d1f9478426..cd7f8ce7a84f 100644
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -1221,7 +1221,13 @@ static const struct mrs_field_value id_aa64pfr0_csv3[] = {
 static const struct mrs_field_value id_aa64pfr0_csv2[] = {
 	MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""),
 	MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"),
-	MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"),
+	MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "CSV2_2"),
+	MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_3, "CSV2_3"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64pfr0_rme[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, RME, NONE, IMPL),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -1239,6 +1245,7 @@ static const struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = {
 static const struct mrs_field_value id_aa64pfr0_amu[] = {
 	MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""),
 	MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"),
+	MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1_1, "AMUv1p1"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -1331,6 +1338,7 @@ static const struct mrs_field_value id_aa64pfr0_el0[] = {
 static const struct mrs_field id_aa64pfr0_fields[] = {
 	MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3),
 	MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2),
+	MRS_FIELD(ID_AA64PFR0, RME, false, MRS_EXACT, id_aa64pfr0_rme),
 	MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, id_aa64pfr0_dit,
 	    id_aa64pfr0_dit_caps),
 	MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu),
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 80828259f23a..b54efffeb8c0 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1089,11 +1089,11 @@
 
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
-#define	ID_AA64PFR0_EL1_op0		0x3
-#define	ID_AA64PFR0_EL1_op1		0x0
-#define	ID_AA64PFR0_EL1_CRn		0x0
-#define	ID_AA64PFR0_EL1_CRm		0x4
-#define	ID_AA64PFR0_EL1_op2		0x0
+#define	ID_AA64PFR0_EL1_op0		3
+#define	ID_AA64PFR0_EL1_op1		0
+#define	ID_AA64PFR0_EL1_CRn		0
+#define	ID_AA64PFR0_EL1_CRm		4
+#define	ID_AA64PFR0_EL1_op2		0
 #define	ID_AA64PFR0_EL0_SHIFT		0
 #define	ID_AA64PFR0_EL0_MASK		(UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
 #define	ID_AA64PFR0_EL0_VAL(x)		((x) & ID_AA64PFR0_EL0_MASK)
@@ -1161,17 +1161,24 @@
 #define	ID_AA64PFR0_AMU_VAL(x)		((x) & ID_AA64PFR0_AMU_MASK)
 #define	 ID_AA64PFR0_AMU_NONE		(UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
 #define	 ID_AA64PFR0_AMU_V1		(UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
+#define	 ID_AA64PFR0_AMU_V1_1		(UL(0x2) << ID_AA64PFR0_AMU_SHIFT)
 #define	ID_AA64PFR0_DIT_SHIFT		48
 #define	ID_AA64PFR0_DIT_MASK		(UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
 #define	ID_AA64PFR0_DIT_VAL(x)		((x) & ID_AA64PFR0_DIT_MASK)
 #define	 ID_AA64PFR0_DIT_NONE		(UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
 #define	 ID_AA64PFR0_DIT_PSTATE		(UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
+#define	ID_AA64PFR0_RME_SHIFT		52
+#define	ID_AA64PFR0_RME_MASK		(UL(0xf) << ID_AA64PFR0_RME_SHIFT)
+#define	ID_AA64PFR0_RME_VAL(x)		((x) & ID_AA64PFR0_RME_MASK)
+#define	 ID_AA64PFR0_RME_NONE		(UL(0x0) << ID_AA64PFR0_RME_SHIFT)
+#define	 ID_AA64PFR0_RME_IMPL		(UL(0x1) << ID_AA64PFR0_RME_SHIFT)
 #define	ID_AA64PFR0_CSV2_SHIFT		56
 #define	ID_AA64PFR0_CSV2_MASK		(UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
 #define	ID_AA64PFR0_CSV2_VAL(x)		((x) & ID_AA64PFR0_CSV2_MASK)
 #define	 ID_AA64PFR0_CSV2_NONE		(UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
 #define	 ID_AA64PFR0_CSV2_ISOLATED	(UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
 #define	 ID_AA64PFR0_CSV2_SCXTNUM	(UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
+#define	 ID_AA64PFR0_CSV2_3		(UL(0x3) << ID_AA64PFR0_CSV2_SHIFT)
 #define	ID_AA64PFR0_CSV3_SHIFT		60
 #define	ID_AA64PFR0_CSV3_MASK		(UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
 #define	ID_AA64PFR0_CSV3_VAL(x)		((x) & ID_AA64PFR0_CSV3_MASK)