From nobody Mon Jan 31 11:32:52 2022 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id EFA941982BD0; Mon, 31 Jan 2022 11:32:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4JnQsd4GyZz3LgX; Mon, 31 Jan 2022 11:32:53 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1643628774; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=TFedmXywFL/mdOgSkM1h/HVhJCA9b9wESUJ9EsWof0Q=; b=NMYT3XwlBQo00hhcSXHchwTxL1sZI5+FgqC+tDtVq2lQ1arJFtxJ02rbMC6Q6khlZjeTHb r6rY0mQOGjfNudaykUNn95gzOXur8xxpWyKR54kkEUyplP0BNpmU8iZRRBFCLB9x4Eg5wd 59EUBpalQnQoF1P+TJRX3LWwN8fG26KiTC2ySVWfDvjw6p2rCx+JoxA7jlGZZYBTjEwYoW 3oOJaciBPCIPhV7hAoXiJ1LAfPIqWWOZofHL+wGjX3G+S79acX9+exMNs659dZiNY1zLSb 1mGXp6ZLpLir3WcMNLoxPJ28vYi6fC9WnzKcoc3KNbzDnHIHO5a7xNr9RkDPjw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A2E841BB01; Mon, 31 Jan 2022 11:32:52 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 20VBWqxB015151; Mon, 31 Jan 2022 11:32:52 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 20VBWq1O015150; Mon, 31 Jan 2022 11:32:52 GMT (envelope-from git) Date: Mon, 31 Jan 2022 11:32:52 GMT Message-Id: <202201311132.20VBWq1O015150@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: 3822a970ff3c - stable/13 - Move instructions into the arm64 exception vectors List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 3822a970ff3c48848e1074a81819fbd57de76bbd Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1643628774; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=TFedmXywFL/mdOgSkM1h/HVhJCA9b9wESUJ9EsWof0Q=; b=RpA+xM2Us9vpCIxh2TdQBWJ0e+svdDgzLPgmOb9cX5Y3ICE+SV6/TDJm9zuchSi5c2Abfu grOdSBoUdSvxEyyxVTUayn3G++KPK7ESM0+9BFCXMhy0vn8rlufDMefMwO0a22hKlVQV0O +oS0dqbVBO77cbVCszkM2EFty9aaeh0RrSZ+hlycVigDSgz8ogg+T3MbRQ8qeE9OUhbq1+ LrDdKhBLFl2iGXnPcf2rxoncRcbgNedRR2cQ+G+sRZmEVSjrLK8gcY8s/iLfvLdbkMWour SZ7dyq5n15IPJrLRAhGIiNL7n+Z+LZgq/gx0G4YG6GDvyrws0dFr7JbMttumaA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1643628774; a=rsa-sha256; cv=none; b=o/MW4cdzSQCwdL5eXgE+/RNxawQK2ZP1wXuaFnxl/C4XEg16gDRuqBl6n+mN/Vz7gIITg5 IOkIuj/80Weg/v0WVIGNVuj6V8Kuf051u4EcgZPfkbkWPKhhYe0zctXU/VOAb84z2GZXvt wUxHdCZkDmCNRYsH5Qav9SVniRiPZ1w6YP34J4DEW19M4hzjuWsZ2Bo+uCg5DO22sTdG6K KwQb6abpfOWzj/5Zh6zWsXC+Vcj4iqhg3KYv42/NGk53o6+axCGwz77APE3+jvWsHWC91z CVO1CqXQMU9dayBbcjozZ4afzyGMe0E4jE+8YZOcLKWgc1ovTcj011wvblXqwA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=3822a970ff3c48848e1074a81819fbd57de76bbd commit 3822a970ff3c48848e1074a81819fbd57de76bbd Author: Andrew Turner AuthorDate: 2022-01-05 15:12:01 +0000 Commit: Andrew Turner CommitDate: 2022-01-31 10:05:47 +0000 Move instructions into the arm64 exception vectors We have 32 instructions in each exception vector on arm64. Previously only one was used to branch to the handler function. We can split the start of these functions and move some of the instructions into the vectors. Reviewed by: kib, markj Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D33751 (cherry picked from commit 77402d2834e64a3530fbaa47d57eccce23c58603) --- sys/arm64/arm64/exception.S | 56 +++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S index 629385c659be..8dd39048226f 100644 --- a/sys/arm64/arm64/exception.S +++ b/sys/arm64/arm64/exception.S @@ -33,7 +33,12 @@ __FBSDID("$FreeBSD$"); .text -.macro save_registers el +/* + * This is limited to 28 instructions as it's placed in the exception vector + * slot that is 32 instructions long. We need one for the branch, and three + * for the prolog. + */ +.macro save_registers_head el .if \el == 1 mov x18, sp sub sp, sp, #128 @@ -66,6 +71,9 @@ __FBSDID("$FreeBSD$"); stp x18, lr, [sp, #(TF_SP)] mrs x18, tpidr_el1 add x29, sp, #(TF_SIZE) +.endm + +.macro save_registers el .if \el == 0 #if defined(PERTHREAD_SSP) /* Load the SSP canary to sp_el0 */ @@ -235,36 +243,40 @@ ENTRY(handle_empty_exception) b 1b END(handle_unhandled_exception) -.macro vempty +.macro vector name, el .align 7 - b handle_empty_exception + save_registers_head \el + b handle_\name + dsb sy + isb + /* Break instruction to ensure we aren't executing code here. */ + brk 0x42 .endm -.macro vector name - .align 7 - b handle_\name +.macro vempty el + vector empty_exception \el .endm .align 11 .globl exception_vectors exception_vectors: - vempty /* Synchronous EL1t */ - vempty /* IRQ EL1t */ - vempty /* FIQ EL1t */ - vempty /* Error EL1t */ + vempty 1 /* Synchronous EL1t */ + vempty 1 /* IRQ EL1t */ + vempty 1 /* FIQ EL1t */ + vempty 1 /* Error EL1t */ - vector el1h_sync /* Synchronous EL1h */ - vector el1h_irq /* IRQ EL1h */ - vempty /* FIQ EL1h */ - vector serror /* Error EL1h */ + vector el1h_sync 1 /* Synchronous EL1h */ + vector el1h_irq 1 /* IRQ EL1h */ + vempty 1 /* FIQ EL1h */ + vector serror 1 /* Error EL1h */ - vector el0_sync /* Synchronous 64-bit EL0 */ - vector el0_irq /* IRQ 64-bit EL0 */ - vempty /* FIQ 64-bit EL0 */ - vector serror /* Error 64-bit EL0 */ + vector el0_sync 0 /* Synchronous 64-bit EL0 */ + vector el0_irq 0 /* IRQ 64-bit EL0 */ + vempty 0 /* FIQ 64-bit EL0 */ + vector serror 0 /* Error 64-bit EL0 */ - vector el0_sync /* Synchronous 32-bit EL0 */ - vector el0_irq /* IRQ 32-bit EL0 */ - vempty /* FIQ 32-bit EL0 */ - vector serror /* Error 32-bit EL0 */ + vector el0_sync 0 /* Synchronous 32-bit EL0 */ + vector el0_irq 0 /* IRQ 32-bit EL0 */ + vempty 0 /* FIQ 32-bit EL0 */ + vector serror 0 /* Error 32-bit EL0 */