git: bb9c3f5121b4 - main - amdiommu: fix typo in the bit description
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Date: Mon, 03 Mar 2025 00:08:33 UTC
The branch main has been updated by kib:
URL: https://cgit.FreeBSD.org/src/commit/?id=bb9c3f5121b42eeda2972d282a54d4eff800297c
commit bb9c3f5121b42eeda2972d282a54d4eff800297c
Author: Konstantin Belousov <kib@FreeBSD.org>
AuthorDate: 2025-03-03 00:06:30 +0000
Commit: Konstantin Belousov <kib@FreeBSD.org>
CommitDate: 2025-03-03 00:08:29 +0000
amdiommu: fix typo in the bit description
Noted by: alc
Sponsored by: Advanced Micro Devices (AMD)
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
---
sys/x86/iommu/amd_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sys/x86/iommu/amd_reg.h b/sys/x86/iommu/amd_reg.h
index 53b8b0cb42fc..fab6d03ea64a 100644
--- a/sys/x86/iommu/amd_reg.h
+++ b/sys/x86/iommu/amd_reg.h
@@ -263,7 +263,7 @@
* IOMMU Extended Feature2 register fields.
* All currently defined bits are RO.
*/
-#define AMDIOMMU_EFR2_TMPMSUP 0x0000000000000004ull /* Tired Mem Migration */
+#define AMDIOMMU_EFR2_TMPMSUP 0x0000000000000004ull /* Tiered Mem Migration */
#define AMDIOMMU_EFR2_GCR3TRPM 0x0000000000000008ull /* GPA based GCR3 pointer in DTE */
#define AMDIOMMU_EFR2_GAPPID 0x0000000000000010ull /* masking of GAPIC PPI */
#define AMDIOMMU_EFR2_SNPAVIC_MASK 0x00000000000000e0ull /* SNP-enabled Adv intr features */