git: eed2b98a2e0c - stable/14 - x86 iommu x86_unit_common: expand hw completion write-out area to 8 bytes

The branch stable/14 has been updated by kib:

URL: https://cgit.FreeBSD.org/src/commit/?id=eed2b98a2e0c9d3ac07e91efba99dab09caf56bd

commit eed2b98a2e0c9d3ac07e91efba99dab09caf56bd
Author:     Konstantin Belousov <kib@FreeBSD.org>
AuthorDate: 2024-06-09 14:08:28 +0000
Commit:     Konstantin Belousov <kib@FreeBSD.org>
CommitDate: 2024-09-11 08:43:59 +0000

    x86 iommu x86_unit_common: expand hw completion write-out area to 8 bytes
    
    (cherry picked from commit fc8da73b93be3f5cc50f7607dbcfc1edb911de65)
---
 sys/x86/iommu/intel_drv.c |  4 ++--
 sys/x86/iommu/x86_iommu.h | 10 ++++++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/sys/x86/iommu/intel_drv.c b/sys/x86/iommu/intel_drv.c
index 9fa1b3f98dc6..66d99748888f 100644
--- a/sys/x86/iommu/intel_drv.c
+++ b/sys/x86/iommu/intel_drv.c
@@ -1302,7 +1302,7 @@ dmar_print_one(int idx, bool show_domains, bool show_mappings)
 			db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
 			    "size 0x%jx\n"
 		    "  head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
-		    "  hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
+		    "  hw compl 0x%jx@%p/phys@%jx next seq 0x%x gen 0x%x\n",
 			    (uintmax_t)unit->x86c.inv_queue,
 			    (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
 			    (uintmax_t)unit->x86c.inv_queue_size,
@@ -1311,7 +1311,7 @@ dmar_print_one(int idx, bool show_domains, bool show_mappings)
 			    unit->x86c.inv_queue_avail,
 			    dmar_read4(unit, DMAR_ICS_REG),
 			    dmar_read4(unit, DMAR_IECTL_REG),
-			    unit->x86c.inv_waitd_seq_hw,
+			    (uintmax_t)unit->x86c.inv_waitd_seq_hw,
 			    &unit->x86c.inv_waitd_seq_hw,
 			    (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys,
 			    unit->x86c.inv_waitd_seq,
diff --git a/sys/x86/iommu/x86_iommu.h b/sys/x86/iommu/x86_iommu.h
index eb1bbafbeb77..966a13c19b6e 100644
--- a/sys/x86/iommu/x86_iommu.h
+++ b/sys/x86/iommu/x86_iommu.h
@@ -101,8 +101,14 @@ struct x86_unit_common {
 	vm_size_t inv_queue_size;
 	uint32_t inv_queue_avail;
 	uint32_t inv_queue_tail;
-	volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait
-					       descr completion */
+
+	/*
+	 * Hw writes there on completion of wait descriptor
+	 * processing.  Intel writes 4 bytes, while AMD does the
+	 * 8-bytes write.  Due to little-endian, and use of 4-byte
+	 * sequence numbers, the difference does not matter for us.
+	 */
+	volatile uint64_t inv_waitd_seq_hw;
 
 	uint64_t inv_waitd_seq_hw_phys;
 	uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */