git: 610348a90467 - main - arm64: add additional MDCR_EL2 fields
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Date: Mon, 09 Sep 2024 16:05:32 UTC
The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=610348a90467980de0498fab8dfdddf221d7a604 commit 610348a90467980de0498fab8dfdddf221d7a604 Author: Zachary Leaf <zachary.leaf@arm.com> AuthorDate: 2024-07-03 07:26:34 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2024-09-09 15:56:53 +0000 arm64: add additional MDCR_EL2 fields Monitor Debug Configuration Register provides EL2 configuration options for self-hosted debug and the Performance Monitors Extension. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46191 --- sys/arm64/include/hypervisor.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h index 1a27a8dd919b..499dba9092fc 100644 --- a/sys/arm64/include/hypervisor.h +++ b/sys/arm64/include/hypervisor.h @@ -267,5 +267,35 @@ #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) #define MDCR_EL2_TDRA_SHIFT 11 #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) +#define MDCR_E2PB_SHIFT 12 +#define MDCR_E2PB_MASK (0x3UL << MDCR_E2PB_SHIFT) +#define MDCR_TPMS_SHIFT 14 +#define MDCR_TPMS (0x1UL << MDCR_TPMS_SHIFT) +#define MDCR_EnSPM_SHIFT 15 +#define MDCR_EnSPM (0x1UL << MDCR_EnSPM_SHIFT) +#define MDCR_HPMD_SHIFT 17 +#define MDCR_HPMD (0x1UL << MDCR_HPMD_SHIFT) +#define MDCR_TTRF_SHIFT 19 +#define MDCR_TTRF (0x1UL << MDCR_TTRF_SHIFT) +#define MDCR_HCCD_SHIFT 23 +#define MDCR_HCCD (0x1UL << MDCR_HCCD_SHIFT) +#define MDCR_E2TB_SHIFT 24 +#define MDCR_E2TB_MASK (0x3UL << MDCR_E2TB_SHIFT) +#define MDCR_HLP_SHIFT 26 +#define MDCR_HLP (0x1UL << MDCR_HLP_SHIFT) +#define MDCR_TDCC_SHIFT 27 +#define MDCR_TDCC (0x1UL << MDCR_TDCC_SHIFT) +#define MDCR_MTPME_SHIFT 28 +#define MDCR_MTPME (0x1UL << MDCR_MTPME_SHIFT) +#define MDCR_HPMFZO_SHIFT 29 +#define MDCR_HPMFZO (0x1UL << MDCR_HPMFZO_SHIFT) +#define MDCR_PMSSE_SHIFT 30 +#define MDCR_PMSSE_MASK (0x3UL << MDCR_PMSSE_SHIFT) +#define MDCR_HPMFZS_SHIFT 36 +#define MDCR_HPMFZS (0x1UL << MDCR_HPMFZS_SHIFT) +#define MDCR_PMEE_SHIFT 40 +#define MDCR_PMEE_MASK (0x3UL << MDCR_PMEE_SHIFT) +#define MDCR_EBWE_SHIFT 43 +#define MDCR_EBWE (0x1UL << MDCR_EBWE_SHIFT) #endif /* !_MACHINE_HYPERVISOR_H_ */