git: 064adb4ba083 - stable/14 - armv8rng: Don't require toolchain to support FEAT_RNG
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Date: Mon, 21 Oct 2024 15:04:59 UTC
The branch stable/14 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=064adb4ba083d00747e3fae6b111545e557ebb1e commit 064adb4ba083d00747e3fae6b111545e557ebb1e Author: Jessica Clarke <jrtc27@FreeBSD.org> AuthorDate: 2023-12-01 23:59:07 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2024-10-21 15:03:26 +0000 armv8rng: Don't require toolchain to support FEAT_RNG We have the mechanism in place to support encoding system registers explicitly, so use that rather than requiring LLVM 13+, which breaks our current set of GitHub CI builds. Fixes: 9eecef052155 ("Add an Armv8 rndr random number provider") (cherry picked from commit 9560ac4b638edf688566f576adc65d3654f2240c) --- sys/arm64/include/armreg.h | 9 +++++++++ sys/dev/random/armv8rng.c | 8 ++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index b96d2223eb0b..e6b5d313a3cf 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2105,6 +2105,15 @@ #define PMXEVTYPER_EL0_CRm 13 #define PMXEVTYPER_EL0_op2 1 +/* RNDRRS */ +#define RNDRRS MRS_REG(RNDRRS) +#define RNDRRS_REG MRS_REG_ALT_NAME(RNDRRS) +#define RNDRRS_op0 3 +#define RNDRRS_op1 3 +#define RNDRRS_CRn 2 +#define RNDRRS_CRm 4 +#define RNDRRS_op2 1 + /* SCTLR_EL1 - System Control Register */ #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ #define SCTLR_M (UL(0x1) << 0) diff --git a/sys/dev/random/armv8rng.c b/sys/dev/random/armv8rng.c index 3cca42a5bbf3..61698bfff820 100644 --- a/sys/dev/random/armv8rng.c +++ b/sys/dev/random/armv8rng.c @@ -59,10 +59,10 @@ random_rndr_read_one(u_long *buf) loop = 10; do { __asm __volatile( - ".arch_extension rng \n" - "mrs %0, rndrrs \n" /* Read the random number */ - "cset %w1, ne \n" /* 1 on success, 0 on failure */ - ".arch_extension norng \n" + /* Read the random number */ + "mrs %0, " __XSTRING(RNDRRS_REG) "\n" + /* 1 on success, 0 on failure */ + "cset %w1, ne\n" : "=&r" (val), "=&r"(ret) :: "cc"); } while (ret != 0 && --loop > 0);