git: 3d0f59024fc0 - stable/14 - e1000: Style pass on if_em
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Date: Wed, 27 Nov 2024 00:29:02 UTC
The branch stable/14 has been updated by kbowling:
URL: https://cgit.FreeBSD.org/src/commit/?id=3d0f59024fc0480a66c34723554ff127ead95f53
commit 3d0f59024fc0480a66c34723554ff127ead95f53
Author: Kevin Bowling <kbowling@FreeBSD.org>
AuthorDate: 2024-11-24 05:45:52 +0000
Commit: Kevin Bowling <kbowling@FreeBSD.org>
CommitDate: 2024-11-27 00:27:45 +0000
e1000: Style pass on if_em
Fix up some indentation and reflow long lines
Sponsored by: BBOX.io
(cherry picked from commit 6f14883066f10afc9e3e2af45c5b509586f9da9e)
---
sys/dev/e1000/if_em.c | 1059 +++++++++++++++++++++++++++++--------------------
1 file changed, 626 insertions(+), 433 deletions(-)
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
index 98521e6e6ee9..c258b23b9d8d 100644
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -53,73 +53,129 @@ static const char igb_driver_version[] = "2.5.28-fbsd";
static const pci_vendor_info_t em_vendor_info_array[] =
{
/* Intel(R) - lem-class legacy devices */
- PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
- PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
- PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
- PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
- PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
-
- PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
- PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
- PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
- PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
- PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
- PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
-
- PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
-
- PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
-
- PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
-
- PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
-
- PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
- PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
-
- PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
- PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
- PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
+ PVID(0x8086, E1000_DEV_ID_82540EM,
+ "Intel(R) Legacy PRO/1000 MT 82540EM"),
+ PVID(0x8086, E1000_DEV_ID_82540EM_LOM,
+ "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
+ PVID(0x8086, E1000_DEV_ID_82540EP,
+ "Intel(R) Legacy PRO/1000 MT 82540EP"),
+ PVID(0x8086, E1000_DEV_ID_82540EP_LOM,
+ "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
+ PVID(0x8086, E1000_DEV_ID_82540EP_LP,
+ "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
+
+ PVID(0x8086, E1000_DEV_ID_82541EI,
+ "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82541ER,
+ "Intel(R) Legacy PRO/1000 82541ER"),
+ PVID(0x8086, E1000_DEV_ID_82541ER_LOM,
+ "Intel(R) Legacy PRO/1000 MT 82541ER"),
+ PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE,
+ "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
+ PVID(0x8086, E1000_DEV_ID_82541GI,
+ "Intel(R) Legacy PRO/1000 MT 82541GI"),
+ PVID(0x8086, E1000_DEV_ID_82541GI_LF,
+ "Intel(R) Legacy PRO/1000 GT 82541PI"),
+ PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE,
+ "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
+
+ PVID(0x8086, E1000_DEV_ID_82542,
+ "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
+
+ PVID(0x8086, E1000_DEV_ID_82543GC_FIBER,
+ "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82543GC_COPPER,
+ "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
+
+ PVID(0x8086, E1000_DEV_ID_82544EI_COPPER,
+ "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82544EI_FIBER,
+ "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82544GC_COPPER,
+ "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82544GC_LOM,
+ "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
+
+ PVID(0x8086, E1000_DEV_ID_82545EM_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82545EM_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82545GM_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82545GM_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82545GM_SERDES,
+ "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
+
+ PVID(0x8086, E1000_DEV_ID_82546EB_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82546EB_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_SERDES,
+ "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_PCIE,
+ "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER,
+ "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
+ "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
+
+ PVID(0x8086, E1000_DEV_ID_82547EI,
+ "Intel(R) Legacy PRO/1000 CT 82547EI"),
+ PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE,
+ "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
+ PVID(0x8086, E1000_DEV_ID_82547GI,
+ "Intel(R) Legacy PRO/1000 CT 82547GI"),
/* Intel(R) - em-class devices */
- PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_COPPER,
+ "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_FIBER,
+ "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_SERDES,
+ "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL,
+ "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD,
+ "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
+ "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP,
+ "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
+ "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
+ "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI,
+ "Intel(R) PRO/1000 PT 82572EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI_COPPER,
+ "Intel(R) PRO/1000 PT 82572EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI_FIBER,
+ "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI_SERDES,
+ "Intel(R) PRO/1000 82572EI (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82573E,
+ "Intel(R) PRO/1000 82573E (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82573E_IAMT,
+ "Intel(R) PRO/1000 82573E AMT (Copper)"),
PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
- PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
+ "Intel(R) 80003ES2LAN (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
+ "Intel(R) 80003ES2LAN (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
+ "Intel(R) 80003ES2LAN (Dual Copper)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
+ "Intel(R) 80003ES2LAN (Dual SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT,
+ "Intel(R) 82566MM ICH8 AMT (Mobile)"),
PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
@@ -127,8 +183,10 @@ static const pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
- PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
- PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
+ PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT,
+ "Intel(R) 82567LM ICH9 AMT"),
+ PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT,
+ "Intel(R) 82566DM-2 ICH9 AMT"),
PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
@@ -152,7 +210,8 @@ static const pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
- PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM,
+ "Intel(R) I218-LM LPTLP"),
PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
@@ -160,57 +219,102 @@ static const pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2,
+ "Intel(R) I219-LM SPT-H(2)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2,
+ "Intel(R) I219-V SPT-H(2)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3,
+ "Intel(R) I219-LM LBG(3)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4,
+ "Intel(R) I219-LM SPT(4)"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5,
+ "Intel(R) I219-LM SPT(5)"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6,
+ "Intel(R) I219-LM CNP(6)"),
PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7,
+ "Intel(R) I219-LM CNP(7)"),
PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8,
+ "Intel(R) I219-LM ICP(8)"),
PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9,
+ "Intel(R) I219-LM ICP(9)"),
PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
- PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
- PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, "Intel(R) I219-LM ADL(19)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, "Intel(R) I219-V ADL(19)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10,
+ "Intel(R) I219-LM CMP(10)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10,
+ "Intel(R) I219-V CMP(10)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11,
+ "Intel(R) I219-LM CMP(11)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11,
+ "Intel(R) I219-V CMP(11)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12,
+ "Intel(R) I219-LM CMP(12)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12,
+ "Intel(R) I219-V CMP(12)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13,
+ "Intel(R) I219-LM TGP(13)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13,
+ "Intel(R) I219-V TGP(13)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14,
+ "Intel(R) I219-LM TGP(14)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14,
+ "Intel(R) I219-V GTP(14)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15,
+ "Intel(R) I219-LM TGP(15)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15,
+ "Intel(R) I219-V TGP(15)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16,
+ "Intel(R) I219-LM ADL(16)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16,
+ "Intel(R) I219-V ADL(16)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17,
+ "Intel(R) I219-LM ADL(17)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17,
+ "Intel(R) I219-V ADL(17)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18,
+ "Intel(R) I219-LM MTP(18)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18,
+ "Intel(R) I219-V MTP(18)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19,
+ "Intel(R) I219-LM ADL(19)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19,
+ "Intel(R) I219-V ADL(19)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20,
+ "Intel(R) I219-LM LNL(20)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20,
+ "Intel(R) I219-V LNL(20)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21,
+ "Intel(R) I219-LM LNL(21)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21,
+ "Intel(R) I219-V LNL(21)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22,
+ "Intel(R) I219-LM RPL(22)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22,
+ "Intel(R) I219-V RPL(22)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23,
+ "Intel(R) I219-LM RPL(23)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23,
+ "Intel(R) I219-V RPL(23)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24,
+ "Intel(R) I219-LM ARL(24)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24,
+ "Intel(R) I219-V ARL(24)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25,
+ "Intel(R) I219-LM PTP(25)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25,
+ "Intel(R) I219-V PTP(25)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26,
+ "Intel(R) I219-LM PTP(26)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26,
+ "Intel(R) I219-V PTP(26)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27,
+ "Intel(R) I219-LM PTP(27)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27,
+ "Intel(R) I219-V PTP(27)"),
/* required last entry */
PVID_END
};
@@ -218,45 +322,68 @@ static const pci_vendor_info_t em_vendor_info_array[] =
static const pci_vendor_info_t igb_vendor_info_array[] =
{
/* Intel(R) - igb-class devices */
- PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82575EB_COPPER,
+ "Intel(R) PRO/1000 82575EB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
+ "Intel(R) PRO/1000 82575EB (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
+ "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
- PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
- PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES,
+ "Intel(R) PRO/1000 82576NS (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82576_FIBER,
+ "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82576_SERDES,
+ "Intel(R) PRO/1000 82576 (Dual SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD,
+ "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER,
+ "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2,
+ "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82576_VF,
+ "Intel(R) PRO/1000 82576 Virtual Function"),
+ PVID(0x8086, E1000_DEV_ID_82580_COPPER,
+ "Intel(R) I340 82580 (Copper)"),
PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82580_SERDES,
+ "Intel(R) I340 82580 (SERDES)"),
PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
- PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
- PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
- PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
+ PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL,
+ "Intel(R) I340-T2 82580 (Dual Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER,
+ "Intel(R) I340-F4 82580 (Quad Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES,
+ "Intel(R) DH89XXCC (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII,
+ "Intel(R) I347-AT4 DH89XXCC"),
PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
- PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
+ PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE,
+ "Intel(R) DH89XXCC (Backplane)"),
PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
- PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT,
+ "Intel(R) I210 IT (Copper)"),
PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
- PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
- PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"),
+ PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS,
+ "Intel(R) I210 Flashless (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS,
+ "Intel(R) I210 Flashless (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS,
+ "Intel(R) I210 Flashless (SGMII)"),
PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
- PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
- PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
+ PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS,
+ "Intel(R) I354 (1.0 GbE Backplane)"),
+ PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS,
+ "Intel(R) I354 (2.5 GbE Backplane)"),
PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
/* required last entry */
PVID_END
@@ -274,8 +401,10 @@ static int em_if_shutdown(if_ctx_t);
static int em_if_suspend(if_ctx_t);
static int em_if_resume(if_ctx_t);
-static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
-static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
+static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
+ int);
+static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
+ int);
static void em_if_queues_free(if_ctx_t);
static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
@@ -517,10 +646,10 @@ SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
-SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
- 0, "Default transmit interrupt delay in usecs");
-SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
- 0, "Default receive interrupt delay in usecs");
+SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN,
+ &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs");
+SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN,
+ &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs");
static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
@@ -532,7 +661,8 @@ SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
"Default receive interrupt delay limit in usecs");
static int em_smart_pwr_down = false;
-SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
+SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN,
+ &em_smart_pwr_down,
0, "Set to true to leave smart power down enabled on newer adapters");
static bool em_unsupported_tso = false;
@@ -589,7 +719,8 @@ static struct if_shared_ctx em_sctx_init = {
.isc_vendor_info = em_vendor_info_array,
.isc_driver_version = em_driver_version,
.isc_driver = &em_if_driver,
- .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
+ .isc_flags =
+ IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
.isc_nrxd_min = {EM_MIN_RXD},
.isc_ntxd_min = {EM_MIN_TXD},
@@ -616,7 +747,8 @@ static struct if_shared_ctx igb_sctx_init = {
.isc_vendor_info = igb_vendor_info_array,
.isc_driver_version = igb_driver_version,
.isc_driver = &igb_if_driver,
- .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
+ .isc_flags =
+ IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
.isc_nrxd_min = {EM_MIN_RXD},
.isc_ntxd_min = {EM_MIN_TXD},
@@ -726,15 +858,21 @@ static int em_get_regs(SYSCTL_HANDLER_ARGS)
for (j = 0; j < nrxd; j++) {
u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
- sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
+ sbuf_printf(sb, "\tReceive Descriptor Address %d: %08"
+ PRIx64 " Error:%d Length:%d\n",
+ j, rxr->rx_base[j].read.buffer_addr, staterr, length);
}
for (j = 0; j < min(ntxd, 256); j++) {
unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
- sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
- j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
- buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
+ sbuf_printf(sb,
+ "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x"
+ " eop: %d DD=%d\n",
+ j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
+ buf->eop != -1 ?
+ txr->tx_base[buf->eop].upper.fields.status &
+ E1000_TXD_STAT_DD : 0);
}
}
@@ -848,7 +986,7 @@ em_if_attach_pre(if_ctx_t ctx)
sc->enable_aim = em_enable_aim;
SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim",
CTLFLAG_RW, &sc->enable_aim, 0,
- "Interrupt Moderation (1=normal, 2=lowlatency)");
+ "Interrupt Moderation (1=normal, 2=lowlatency)");
SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
@@ -896,14 +1034,17 @@ em_if_attach_pre(if_ctx_t ctx)
"TSO TCP flags mask for last segment");
scctx->isc_tx_nsegments = EM_MAX_SCATTER;
- scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
+ scctx->isc_nrxqsets_max =
+ scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
if (bootverbose)
device_printf(dev, "attach_pre capping queues at %d\n",
scctx->isc_ntxqsets_max);
if (hw->mac.type >= igb_mac_min) {
- scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
- scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
+ scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
+ sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
+ scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
+ sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
scctx->isc_txrx = &igb_txrx;
@@ -922,8 +1063,10 @@ em_if_attach_pre(if_ctx_t ctx)
*/
scctx->isc_msix_bar = pci_msix_table_bar(dev);
} else if (hw->mac.type >= em_mac_min) {
- scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
- scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
+ scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
+ sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
+ scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
+ sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
scctx->isc_txrx = &em_txrx;
@@ -934,11 +1077,12 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
CSUM_IP6_TCP | CSUM_IP6_UDP;
- /* Disable TSO on all em(4) until ring stalls can be debugged */
+ /* Disable TSO on all em(4) until ring stalls are debugged */
scctx->isc_capenable &= ~IFCAP_TSO;
/*
- * Disable TSO on SPT due to errata that downclocks DMA performance
+ * Disable TSO on SPT due to errata that downclocks DMA
+ * performance
* i218-i219 Specification Update 1.5.4.5
*/
if (hw->mac.type == e1000_pch_spt)
@@ -955,8 +1099,10 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_disable_msix = 1;
}
} else {
- scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
- scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
+ scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) *
+ sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
+ scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) *
+ sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
scctx->isc_txrx = &lem_txrx;
@@ -969,7 +1115,7 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
CSUM_IP6_TCP | CSUM_IP6_UDP;
- /* Disable TSO on all lem(4) until ring stalls can be debugged */
+ /* Disable TSO on all lem(4) until ring stalls debugged */
scctx->isc_capenable &= ~IFCAP_TSO;
/* 82541ER doesn't do HW tagging */
@@ -980,15 +1126,18 @@ em_if_attach_pre(if_ctx_t ctx)
}
/* This is the first e1000 chip and it does not do offloads */
if (hw->mac.type == e1000_82542) {
- scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
- IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING |
- IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO);
+ scctx->isc_capabilities &= ~(IFCAP_HWCSUM |
+ IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 |
+ IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
+ IFCAP_TSO | IFCAP_VLAN_HWTSO);
scctx->isc_capenable = scctx->isc_capabilities;
}
/* These can't do TSO for various reasons */
- if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 ||
+ if (hw->mac.type < e1000_82544 ||
+ hw->mac.type == e1000_82547 ||
hw->mac.type == e1000_82547_rev_2) {
- scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO);
+ scctx->isc_capabilities &=
+ ~(IFCAP_TSO |IFCAP_VLAN_HWTSO);
scctx->isc_capenable = scctx->isc_capabilities;
}
/* XXXKB: No IPv6 before this? */
@@ -996,10 +1145,14 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6;
scctx->isc_capenable = scctx->isc_capabilities;
}
- /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */
- if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2)
- scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
- IFCAP_HWCSUM_IPV6);
+ /*
+ * "PCI/PCI-X SDM 4.0" page 33 (b):
+ * FDX requirement on these chips
+ */
+ if (hw->mac.type == e1000_82547 ||
+ hw->mac.type == e1000_82547_rev_2)
+ scctx->isc_capenable &= ~(IFCAP_HWCSUM |
+ IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6);
/* INTx only */
scctx->isc_msix_bar = 0;
@@ -1046,11 +1199,9 @@ em_if_attach_pre(if_ctx_t ctx)
** FLASH read/write macros in the shared code.
*/
else if (hw->mac.type >= e1000_pch_spt) {
- sc->osdep.flash_bus_space_tag =
- sc->osdep.mem_bus_space_tag;
+ sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag;
sc->osdep.flash_bus_space_handle =
- sc->osdep.mem_bus_space_handle
- + E1000_FLASH_BASE_ADDR;
+ sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR;
}
/* Do Shared Code initialization */
@@ -1076,15 +1227,17 @@ em_if_attach_pre(if_ctx_t ctx)
}
if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) {
em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
- "receive interrupt delay limit in usecs", &sc->rx_abs_int_delay,
+ "receive interrupt delay limit in usecs",
+ &sc->rx_abs_int_delay,
E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt);
em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
- "transmit interrupt delay limit in usecs", &sc->tx_abs_int_delay,
+ "transmit interrupt delay limit in usecs",
+ &sc->tx_abs_int_delay,
E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt);
em_add_int_delay_sysctl(sc, "itr",
"interrupt delay limit in usecs/4", &sc->tx_itr,
E1000_REGISTER(hw, E1000_ITR),
- EM_INTS_TO_ITR(em_max_interrupt_rate));
+ EM_INTS_TO_ITR(em_max_interrupt_rate));
}
hw->mac.autoneg = DO_AUTO_NEG;
@@ -1119,7 +1272,8 @@ em_if_attach_pre(if_ctx_t ctx)
sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
if (sc->mta == NULL) {
- device_printf(dev, "Can not allocate multicast setup array\n");
+ device_printf(dev,
+ "Can not allocate multicast setup array\n");
error = ENOMEM;
goto err_late;
}
@@ -1129,8 +1283,8 @@ em_if_attach_pre(if_ctx_t ctx)
/* Check SOL/IDER usage */
if (e1000_check_reset_block(hw))
- device_printf(dev, "PHY reset is blocked"
- " due to SOL/IDER session.\n");
+ device_printf(dev,
+ "PHY reset is blocked due to SOL/IDER session.\n");
/* Sysctl for setting Energy Efficient Ethernet */
if (hw->mac.type < igb_mac_min)
@@ -1165,8 +1319,8 @@ em_if_attach_pre(if_ctx_t ctx)
/* Copy the permanent MAC address out of the EEPROM */
if (e1000_read_mac_addr(hw) < 0) {
- device_printf(dev, "EEPROM read error while reading MAC"
- " address\n");
+ device_printf(dev,
+ "EEPROM read error while reading MAC address\n");
error = EIO;
goto err_late;
}
@@ -1241,7 +1395,10 @@ em_if_attach_post(if_ctx_t ctx)
return (0);
err_late:
- /* upon attach_post() error, iflib calls _if_detach() to free resources. */
+ /*
+ * Upon em_if_attach_post() error, iflib calls em_if_detach() to
+ * free resources
+ */
return (error);
}
@@ -1383,8 +1540,7 @@ em_if_init(if_ctx_t ctx)
INIT_DEBUGOUT("em_if_init: begin");
/* Get the latest mac address, User can use a LAA */
- bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
- ETHER_ADDR_LEN);
+ bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
/* Put the address into the Receive Address Array */
e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
@@ -1405,7 +1561,8 @@ em_if_init(if_ctx_t ctx)
em_reset(ctx);
em_if_update_admin_status(ctx);
- for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) {
+ for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues;
+ i++, tx_que++) {
struct tx_ring *txr = &tx_que->txr;
txr->tx_rs_cidx = txr->tx_rs_pidx;
@@ -1452,8 +1609,10 @@ em_if_init(if_ctx_t ctx)
E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
/* Set the IVAR - interrupt vector routing. */
E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
- } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
+ } else if (sc->intr_type == IFLIB_INTR_MSIX) {
+ /* Set up queue routing */
igb_configure_queues(sc);
+ }
/* this clears any pending interrupts */
E1000_READ_REG(&sc->hw, E1000_ICR);
@@ -1516,7 +1675,7 @@ em_newitr(struct e1000_softc *sc, struct em_rx_queue *que,
goto em_set_next_itr;
}
- /* Get the largest values from the associated tx and rx ring */
+ /* Get largest values from the associated tx and rx ring */
if (txr->tx_bytes && txr->tx_packets) {
bytes = txr->tx_bytes;
bytes_packets = txr->tx_bytes/txr->tx_packets;
@@ -1524,7 +1683,8 @@ em_newitr(struct e1000_softc *sc, struct em_rx_queue *que,
}
if (rxr->rx_bytes && rxr->rx_packets) {
bytes = max(bytes, rxr->rx_bytes);
- bytes_packets = max(bytes_packets, rxr->rx_bytes/rxr->rx_packets);
+ bytes_packets =
+ max(bytes_packets, rxr->rx_bytes/rxr->rx_packets);
packets = max(packets, rxr->rx_packets);
}
@@ -1545,7 +1705,8 @@ em_newitr(struct e1000_softc *sc, struct em_rx_queue *que,
/* Handle TSO */
if (bytes_packets > 8000)
nextlatency = itr_latency_bulk;
- else if ((packets < 10) || (bytes_packets > 1200))
+ else if ((packets < 10) ||
+ (bytes_packets > 1200))
nextlatency = itr_latency_bulk;
else if (packets > 35)
nextlatency = itr_latency_lowest;
@@ -1564,8 +1725,8 @@ em_newitr(struct e1000_softc *sc, struct em_rx_queue *que,
break;
default:
nextlatency = itr_latency_low;
- device_printf(sc->dev, "Unexpected newitr transition %d\n",
- nextlatency);
+ device_printf(sc->dev,
+ "Unexpected newitr transition %d\n", nextlatency);
break;
}
@@ -1609,7 +1770,8 @@ em_set_next_itr:
if (newitr != que->itr_setting) {
que->itr_setting = newitr;
- E1000_WRITE_REG(hw, E1000_EITR(que->msix), que->itr_setting);
+ E1000_WRITE_REG(hw, E1000_EITR(que->msix),
+ que->itr_setting);
}
} else {
newitr = EM_INTS_TO_ITR(newitr);
@@ -1618,9 +1780,11 @@ em_set_next_itr:
que->itr_setting = newitr;
if (hw->mac.type == e1000_82574 && que->msix) {
E1000_WRITE_REG(hw,
- E1000_EITR_82574(que->msix), que->itr_setting);
+ E1000_EITR_82574(que->msix),
+ que->itr_setting);
} else {
- E1000_WRITE_REG(hw, E1000_ITR, que->itr_setting);
+ E1000_WRITE_REG(hw, E1000_ITR,
+ que->itr_setting);
}
}
}
@@ -1779,8 +1943,8 @@ em_msix_link(void *arg)
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
} else if (sc->hw.mac.type == e1000_82574) {
- E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
- E1000_IMS_OTHER);
+ E1000_WRITE_REG(&sc->hw, E1000_IMS,
+ E1000_IMS_LSC | E1000_IMS_OTHER);
/*
* Because we must read the ICR for this interrupt it may
* clear other causes using autoclear, for this reason we
@@ -1923,7 +2087,8 @@ em_if_set_promisc(if_ctx_t ctx, int flags)
if (flags & IFF_ALLMULTI)
mcnt = MAX_NUM_MULTICAST_ADDRESSES;
else
- mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
+ mcnt = min(if_llmaddr_count(ifp),
+ MAX_NUM_MULTICAST_ADDRESSES);
if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
reg_rctl &= (~E1000_RCTL_MPE);
@@ -1972,7 +2137,7 @@ em_if_multi_set(if_ctx_t ctx)
{
struct e1000_softc *sc = iflib_get_softc(ctx);
if_t ifp = iflib_get_ifp(ctx);
- u8 *mta; /* Multicast array memory */
+ u8 *mta; /* Multicast array memory */
u32 reg_rctl = 0;
int mcnt = 0;
@@ -2031,7 +2196,6 @@ em_if_multi_set(if_ctx_t ctx)
static void
em_if_timer(if_ctx_t ctx, uint16_t qid)
{
-
if (qid != 0)
return;
@@ -2065,8 +2229,8 @@ em_if_update_admin_status(if_ctx_t ctx)
break;
case e1000_media_type_fiber:
e1000_check_for_link(hw);
- link_check = (E1000_READ_REG(hw, E1000_STATUS) &
- E1000_STATUS_LU);
+ link_check =
+ (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
break;
case e1000_media_type_internal_serdes:
e1000_check_for_link(hw);
@@ -2123,11 +2287,11 @@ em_if_update_admin_status(if_ctx_t ctx)
sc->flags |= IGB_MEDIA_RESET;
em_reset(ctx);
}
- /* Only do TSO on gigabit Ethernet for older chips due to errata */
+ /* Only do TSO on gigabit for older chips due to errata */
if (hw->mac.type < igb_mac_min)
automasked = em_automask_tso(ctx);
- /* Automasking resets the interface, so don't mark it up yet */
+ /* Automasking resets the interface so don't mark it up yet */
if (!automasked)
iflib_link_state_change(ctx, LINK_STATE_UP,
IF_Mbps(sc->link_speed));
@@ -2202,10 +2366,8 @@ em_identify_hardware(if_ctx_t ctx)
sc->hw.vendor_id = pci_get_vendor(dev);
sc->hw.device_id = pci_get_device(dev);
sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
- sc->hw.subsystem_vendor_id =
- pci_read_config(dev, PCIR_SUBVEND_0, 2);
- sc->hw.subsystem_device_id =
- pci_read_config(dev, PCIR_SUBDEV_0, 2);
+ sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
+ sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
/* Do Shared Code Init and Setup */
if (e1000_set_mac_type(&sc->hw)) {
@@ -2229,15 +2391,15 @@ em_allocate_pci_resources(if_ctx_t ctx)
int rid, val;
rid = PCIR_BAR(0);
- sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &rid, RF_ACTIVE);
+ sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
if (sc->memory == NULL) {
- device_printf(dev, "Unable to allocate bus resource: memory\n");
+ device_printf(dev,
+ "Unable to allocate bus resource: memory\n");
return (ENXIO);
}
sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
- sc->osdep.mem_bus_space_handle =
- rman_get_bushandle(sc->memory);
+ sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
/* Only older adapters use IO mapping */
@@ -2260,8 +2422,8 @@ em_allocate_pci_resources(if_ctx_t ctx)
sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&rid, RF_ACTIVE);
if (sc->ioport == NULL) {
- device_printf(dev, "Unable to allocate bus resource: "
- "ioport\n");
+ device_printf(dev,
+ "Unable to allocate bus resource: ioport\n");
return (ENXIO);
}
sc->hw.io_base = 0;
@@ -2294,9 +2456,12 @@ em_if_msix_intr_assign(if_ctx_t ctx, int msix)
for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
rid = vector + 1;
snprintf(buf, sizeof(buf), "rxq%d", i);
- error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
+ error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
+ IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
if (error) {
- device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
+ device_printf(iflib_get_dev(ctx),
+ "Failed to allocate que int %d err: %d",
+ i, error);
sc->rx_num_queues = i + 1;
goto fail;
}
@@ -2349,10 +2514,12 @@ em_if_msix_intr_assign(if_ctx_t ctx, int msix)
*** 891 LINES SKIPPED ***