From nobody Mon Nov 25 21:08:46 2024 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4XxyxB4DPFz5fCQS; Mon, 25 Nov 2024 21:08:46 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4XxyxB2xY5z4tp6; Mon, 25 Nov 2024 21:08:46 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1732568926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dF/lf9tcdIIovirjFc1t3EGP9bZpQ4C4bQeZgpnEiSU=; b=e4vyY8d05IRT/0zhbGs2p6HrR4/fg5hXVscfecWvKZ6kZSj+NIvcec0niJgA3wGDRJQ2JH Yw2UOue0XkXZIyyXNUVVPlFiHqLrnGPD6UmS3SHAeGL6suqCVdIKz4XSzu+OSeWcLdPKGd PBg8eLrklkqDhwVypSbiGGdWPArZHUd40R2wJVqA44WzZ8Z0l8O3Cvw9+LPzh+FrBBDnEQ lrS9hGSqrPo5wD62tkDHDSvoXpPkU31522VZefd79ZieRQ6B/gRtuJn90eahS743O1C9tK 5UahY7evTcYP1MS/Xa2B82eRF5g33almeQ+gBfjliD8pvzBIl36CK1y+KR+S/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1732568926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dF/lf9tcdIIovirjFc1t3EGP9bZpQ4C4bQeZgpnEiSU=; b=aqpSdyxhWnDaPQirxvBdfnEDS8tyFJvTUeTtjPZ7QVe7lJlUQJtIT9+X09A9X0dctGhBx8 zd1iT9TAF6wHx2eA1FNLG9MfcLMxdXcQpTtFxybwrILH8Dj/wWf/ud9CqmIchbxqlA1W6W d/ZZJrnsM9UoWt55P65WkXKLprGqRXKaS+G3Z7VaqoTb0XFqV8Bzrhb3jaZ+EQUI1n9V9Q xHfspcNohFnGa8N7ZBV7K9HvoTcmx9TZQd/B5limZ434+B6JmjWeFNtXoXy3kQDUzvfsTh RkrjMXANHP5Snw4FIXEaQHPxHioMwbmHV8WjXdHifvUosy86w8En8aZXw2RjaA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1732568926; a=rsa-sha256; cv=none; b=ynawOGiZ7NkYdUZgpch+7TyHGbSY2Yg9hzsLzj0Cma80lvlsb9JgqEK3/b1Wo/ApMlmRBG 3nVuraySH33CXo48NDx9YmdT/2vU6ggSKUd1SyU8R2XquDL3dMw8VFCJdsUoCTCtmPVeY3 T8pNthEqwsxLzJzNEch9SCA7zXYtqL7uZkfjkgk7nO336nBnUlnnwLqYc5y1UKI4emKMUI 259wmjFLxWv32TGKQ79+pRGI3zgTMSresnUt846BNjqZtyPMj6x2b+ntanj41WE10LG4zY wjr9vk2UisXDNImRxBZU3k6PuN1Gh8NP7PnleczlsEVyOUwkfvlek3laSMcGcA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4XxyxB2Xc6zwKH; Mon, 25 Nov 2024 21:08:46 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 4APL8kOE011405; Mon, 25 Nov 2024 21:08:46 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 4APL8kA0011402; Mon, 25 Nov 2024 21:08:46 GMT (envelope-from git) Date: Mon, 25 Nov 2024 21:08:46 GMT Message-Id: <202411252108.4APL8kA0011402@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: dfe57951f061 - main - riscv: add custom T-HEAD dcache ops List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: dfe57951f0610c6de42190b32c7ed844a97ee593 Auto-Submitted: auto-generated The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=dfe57951f0610c6de42190b32c7ed844a97ee593 commit dfe57951f0610c6de42190b32c7ed844a97ee593 Author: Mitchell Horne AuthorDate: 2024-11-21 18:11:51 +0000 Commit: Mitchell Horne CommitDate: 2024-11-25 21:08:04 +0000 riscv: add custom T-HEAD dcache ops This is the first major quirk we need to support in order to run on current T-HEAD/XuanTie CPUs, e.g. the C906 or C910, found in several existing RISC-V SBCs. With these custom dcache routines installed, busdma can reliably communicate with devices which are not coherent w.r.t. the CPU's data caches. This patch introduces the first quirk/errata handling functions to identcpu.c, and thus is forced to make some decisions about how this code is structured. It will be amended with the changes that follow in the series, yet I feel the final result is (unavoidably) somewhat clumsy. I expect the CPU identification code will continue to evolve as more CPUs and their quirks are eventually supported. Discussed with: jrtc27 Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D47455 --- sys/conf/files.riscv | 2 + sys/riscv/include/thead.h | 35 ++++++++++++++++ sys/riscv/riscv/identcpu.c | 21 ++++++++++ sys/riscv/thead/thead.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 157 insertions(+) diff --git a/sys/conf/files.riscv b/sys/conf/files.riscv index 915bce34603d..6186ae9b3371 100644 --- a/sys/conf/files.riscv +++ b/sys/conf/files.riscv @@ -84,5 +84,7 @@ riscv/vmm/vmm_riscv.c optional vmm riscv/vmm/vmm_sbi.c optional vmm riscv/vmm/vmm_switch.S optional vmm +riscv/thead/thead.c standard + # Zstd contrib/zstd/lib/freebsd/zstd_kfreebsd.c optional zstdio compile-with ${ZSTD_C} diff --git a/sys/riscv/include/thead.h b/sys/riscv/include/thead.h new file mode 100644 index 000000000000..e11d5c37374c --- /dev/null +++ b/sys/riscv/include/thead.h @@ -0,0 +1,35 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 The FreeBSD Foundation + * + * This software was developed by Mitchell Horne under + * sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _RISCV_THEAD_H_ +#define _RISCV_THEAD_H_ + +void thead_setup_cache(void); + +#endif /* _RISCV_THEAD_H_ */ diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c index 7823830c3136..f85aed88d3b9 100644 --- a/sys/riscv/riscv/identcpu.c +++ b/sys/riscv/riscv/identcpu.c @@ -52,6 +52,7 @@ #include #include #include +#include #ifdef FDT #include @@ -463,6 +464,25 @@ identify_cpu_ids(struct cpu_desc *desc) } } +static void +handle_thead_quirks(u_int cpu, struct cpu_desc *desc) +{ + if (cpu != 0) + return; + + thead_setup_cache(); +} + +static void +handle_cpu_quirks(u_int cpu, struct cpu_desc *desc) +{ + switch (mvendorid) { + case MVENDORID_THEAD: + handle_thead_quirks(cpu, desc); + break; + } +} + void identify_cpu(u_int cpu) { @@ -472,6 +492,7 @@ identify_cpu(u_int cpu) identify_cpu_features(cpu, desc); update_global_capabilities(cpu, desc); + handle_cpu_quirks(cpu, desc); } void diff --git a/sys/riscv/thead/thead.c b/sys/riscv/thead/thead.c new file mode 100644 index 000000000000..f959d32cfed8 --- /dev/null +++ b/sys/riscv/thead/thead.c @@ -0,0 +1,99 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 The FreeBSD Foundation + * + * This software was developed by Mitchell Horne under + * sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include +#include + +#include + +/* ----------------- dcache ops --------------------- */ + + +/* th.dcache.civa: clean & invalidate at VA stored in t0. */ +#define THEAD_DCACHE_CIVA ".long 0x0272800b\n" + +/* th.dcache.iva: invalidate at VA stored in t0. */ +#define THEAD_DCACHE_IVA ".long 0x0262800b\n" + +/* th.dcache.cva: clean at VA stored in t0. */ +#define THEAD_DCACHE_CVA ".long 0x0252800b\n" + +/* th.sync.s: two-way instruction barrier */ +#define THEAD_SYNC_S ".long 0x0190000b\n" + +/* MHTODO: we could parse this information from the device tree. */ +#define THEAD_DCACHE_SIZE 64 + +static void +thead_cpu_dcache_wbinv_range(vm_offset_t va, vm_size_t len) +{ + register vm_offset_t t0 __asm("t0") = rounddown(va, dcache_line_size); + + for (; t0 < va + len; t0 += dcache_line_size) { + __asm __volatile(THEAD_DCACHE_CIVA + :: "r" (t0) : "memory"); + } + __asm __volatile(THEAD_SYNC_S ::: "memory"); +} + +static void +thead_cpu_dcache_inv_range(vm_offset_t va, vm_size_t len) +{ + register vm_offset_t t0 __asm("t0") = rounddown(va, dcache_line_size); + + for (; t0 < va + len; t0 += dcache_line_size) { + __asm __volatile(THEAD_DCACHE_IVA + :: "r" (t0) : "memory"); + } + __asm __volatile(THEAD_SYNC_S ::: "memory"); +} + +static void +thead_cpu_dcache_wb_range(vm_offset_t va, vm_size_t len) +{ + register vm_offset_t t0 __asm("t0") = rounddown(va, dcache_line_size); + + for (; t0 < va + len; t0 += dcache_line_size) { + __asm __volatile(THEAD_DCACHE_CVA + :: "r" (t0) : "memory"); + } + __asm __volatile(THEAD_SYNC_S ::: "memory"); +} + +void +thead_setup_cache(void) +{ + struct riscv_cache_ops thead_ops; + + thead_ops.dcache_wbinv_range = thead_cpu_dcache_wbinv_range; + thead_ops.dcache_inv_range = thead_cpu_dcache_inv_range; + thead_ops.dcache_wb_range = thead_cpu_dcache_wb_range; + + riscv_cache_install_hooks(&thead_ops, THEAD_DCACHE_SIZE); +}