From nobody Fri Nov 08 22:12:48 2024 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4XlY8w6nlVz5csRg; Fri, 08 Nov 2024 22:12:48 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4XlY8w6Gzzz4SGX; Fri, 8 Nov 2024 22:12:48 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1731103968; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=s63tWWu50uGuamoX2bcOLhZVnaySwXXGL1SEDJDepx8=; b=Bq61UQvvQ1+JjqRZ1ofG73cPtcXR0KmgIZbCCSe0rix/RvOWnLcjnCloFUCkkqoDv718Mh hqemkCFMuREv4He+OLQ3wGQqqPE/fU6CzoPBfsL0c53fWqKZOPZTVFDBjhBOhZ+nipfzrm 9cUYlF/BEXg7DG1GVB0C35wbCRanPEZl9S1b9mwS41PuUA3YfGxbQJlEcUyg+1C/OKIoFQ nIq172rNruod6Y1T+axAZ/y2RN4+AHmFIAem1Jydr03ecnVbO78yPz+z4I9IH24C3ofnvs 1j10JBc6QF8kVLhikpkW+TtT+ZpPKIanmk221nTCzCYaHCP4ayG5SfPteWYneg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1731103968; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=s63tWWu50uGuamoX2bcOLhZVnaySwXXGL1SEDJDepx8=; b=esx4B/JFYkl+pJn9d4IfZ6nlMKwldSr9Jme35YpEgNYNoKOEJWCLmH5g0a8EaTBXYLMQ04 nbhYwo5WtJAJL1it8n0yo3mtJE0uGequRtzTJ7vlnCI5kE8zbtNVeWPb2hEjL2dwtsrVln xqN5qj9Dk0uIK42CJiOlx86sxdVZJrHLAn5LM05LCbAO1ZSwsGuebFo7+BvZC9yP1iIjIi 4PWFNvSebAyQBAU6rRa6C8MBThq+hpRjqCjr28b2WY6eNtmUpRNZhMfWvtI1iv/ViKC335 656PEKuVqdILv3Upt4d1EpkqKrBz5KiYVopzMLlYiy72A5H1OCEBqhHVtmfodw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1731103968; a=rsa-sha256; cv=none; b=fqPFVO2GHKk396TqwdYmeEX4wz+ZSGtKZyVS6rSDEx2x98sURSX++GsTXpKUhDrQEWlQFn gOClY4ch6kp/031kZ6q5i21FrNOmgd40IjqbMPFJd01oj9kdsh0JKnVOb95hZfjWBkZBwa OLkwFrrIaUA4q45ErvpdVPEBJNmKIjaPW6l7WYTWbh+aFHXDbQwvwPMZ/D1JHMs90SDLfP 8TAacL66ZfjM2mMKPQ+9Tt9AvC7v8e5IDzosdyfihhdN/bFuw7H8AxzsTTLl7CRzMgK+Up JzdeYd9A/dWcySnN7zi8ysPsb/oNjYOl9Tc2eRBlYtYKg5UCXdfOxjTYDnYbww== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4XlY8w5tS6znP1; Fri, 8 Nov 2024 22:12:48 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 4A8MCmGD080910; Fri, 8 Nov 2024 22:12:48 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 4A8MCmsw080907; Fri, 8 Nov 2024 22:12:48 GMT (envelope-from git) Date: Fri, 8 Nov 2024 22:12:48 GMT Message-Id: <202411082212.4A8MCmsw080907@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Gallatin Subject: git: fd67ff5c7a6c - main - Use the correct idle routine on recent AMD EPYC servers List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: gallatin X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: fd67ff5c7a6cd9a2e82e6a02ea249cec76a4c030 Auto-Submitted: auto-generated The branch main has been updated by gallatin: URL: https://cgit.FreeBSD.org/src/commit/?id=fd67ff5c7a6cd9a2e82e6a02ea249cec76a4c030 commit fd67ff5c7a6cd9a2e82e6a02ea249cec76a4c030 Author: Andrew Gallatin AuthorDate: 2024-11-08 21:37:32 +0000 Commit: Andrew Gallatin CommitDate: 2024-11-08 22:10:44 +0000 Use the correct idle routine on recent AMD EPYC servers We have been incorrectly choosing the "hlt" idle method on modern AMD EPYC servers for C1 idle. This is because AMD also uses the Functional Fixed Hardware interface. Due to not parsing the table properly for AMD, and due to a weird quirk where the mwait latency for C1 is mis-interpreted as the latency for hlt, we wind up choosing hlt for c1, which has a far higher wake up latency (similar to IO) of roughly 400us on my test system (AMD 7502P). This patch fixes this by: - Looking for AMD in addition to Intel in the FFH (Note the vendor id of "2" for AMD is not publically documented, but AMD has confirmed they are using "2" and has promised to document it.) - Using mwait on AMD when specified in the table, and when CPUid says its supported - Fixing a weird issue where we copy the contents of cx_ptr for C1 and when moving to C2, we do not reinitialize cx_ptr. This leads to mwait being selected, and ignoring the specified i/o halt method unless we clear mwait before looking at the table for C2. Differential Revision: https://reviews.freebsd.org/D47444 Reviewed by: dab, kib, vangyzen Sponsored by: Netflix --- sys/dev/acpica/acpi_cpu.c | 9 +++++++-- sys/x86/include/x86_var.h | 1 + sys/x86/x86/identcpu.c | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/sys/dev/acpica/acpi_cpu.c b/sys/dev/acpica/acpi_cpu.c index 80855cf168e9..63e17de1ff28 100644 --- a/sys/dev/acpica/acpi_cpu.c +++ b/sys/dev/acpica/acpi_cpu.c @@ -131,6 +131,7 @@ struct acpi_cpu_device { #define PIIX4_PCNTRL_BST_EN (1<<10) #define CST_FFH_VENDOR_INTEL 1 +#define CST_FFH_VENDOR_AMD 2 #define CST_FFH_INTEL_CL_C1IO 1 #define CST_FFH_INTEL_CL_MWAIT 2 #define CST_FFH_MWAIT_HW_COORD 0x0001 @@ -855,7 +856,8 @@ acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); #if defined(__i386__) || defined(__amd64__) if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, - &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { + &accsize) == 0 && + (vendor == CST_FFH_VENDOR_INTEL || vendor == CST_FFH_VENDOR_AMD)) { if (class == CST_FFH_INTEL_CL_C1IO) { /* C1 I/O then Halt */ cx_ptr->res_rid = sc->cpu_cx_count; @@ -872,7 +874,9 @@ acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) "degrading to C1 Halt", (int)address); } } else if (class == CST_FFH_INTEL_CL_MWAIT) { - acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); + if (vendor == CST_FFH_VENDOR_INTEL || + (vendor == CST_FFH_VENDOR_AMD && cpu_mon_mwait_edx != 0)) + acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); } } #endif @@ -922,6 +926,7 @@ acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); if (cx_ptr->p_lvlx) { + cx_ptr->do_mwait = false; ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: Got C%d - %d latency\n", device_get_unit(sc->cpu_dev), cx_ptr->type, diff --git a/sys/x86/include/x86_var.h b/sys/x86/include/x86_var.h index f19c557e270b..6609871bf89e 100644 --- a/sys/x86/include/x86_var.h +++ b/sys/x86/include/x86_var.h @@ -62,6 +62,7 @@ extern char cpu_vendor[]; extern char cpu_model[]; extern u_int cpu_vendor_id; extern u_int cpu_mon_mwait_flags; +extern u_int cpu_mon_mwait_edx; extern u_int cpu_mon_min_size; extern u_int cpu_mon_max_size; extern u_int cpu_maxphyaddr; diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c index d3aec5b5e0c6..3f8f11fda011 100644 --- a/sys/x86/x86/identcpu.c +++ b/sys/x86/x86/identcpu.c @@ -117,6 +117,7 @@ u_int cpu_stdext_feature3; /* %edx */ uint64_t cpu_ia32_arch_caps; u_int cpu_max_ext_state_size; u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ +u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */ u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ u_int cpu_maxphyaddr; /* Max phys addr width in bits */ @@ -1634,6 +1635,7 @@ finishidentcpu(void) if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { do_cpuid(5, regs); cpu_mon_mwait_flags = regs[2]; + cpu_mon_mwait_edx = regs[3]; cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; }