git: 10b3eac88db6 - main - arm64: add PMBSR_MSS_{BSC,FSC} status code field

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=10b3eac88db689d657c4d0d0716bcbdf240ff614

commit 10b3eac88db689d657c4d0d0716bcbdf240ff614
Author:     Zachary Leaf <zachary.leaf@arm.com>
AuthorDate: 2023-09-20 09:51:22 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2024-05-17 14:46:00 +0000

    arm64: add PMBSR_MSS_{BSC,FSC} status code field
    
    Bits [5:0] of PMBSR_MSS encodes either Buffer Status Code (BSC) or Fault
    Status Code (FSC) depending on PMBSR_EC value.
    
    Add PMBSR_MSS_{BSC,FSC} to cover this field.
    
    Reviewed by:    andrew
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D45172
---
 sys/arm64/include/armreg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 144e357d14b2..ccd9f4a5c78a 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1689,6 +1689,8 @@
 #define	PMBSR_EL1_op2			3
 #define	PMBSR_MSS_SHIFT			0
 #define	PMBSR_MSS_MASK			(UL(0xffff) << PMBSR_MSS_SHIFT)
+#define	PMBSR_MSS_BSC_MASK		(UL(0x3f) << PMBSR_MSS_SHIFT)
+#define	PMBSR_MSS_FSC_MASK		(UL(0x3f) << PMBSR_MSS_SHIFT)
 #define	PMBSR_COLL_SHIFT		16
 #define	PMBSR_COLL			(UL(0x1) << PMBSR_COLL_SHIFT)
 #define	PMBSR_S_SHIFT			17