From nobody Mon Jul 15 12:38:22 2024 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4WN1vg2brRz5QrdK; Mon, 15 Jul 2024 12:38:23 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R11" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4WN1vf5Qnwz4Hm6; Mon, 15 Jul 2024 12:38:22 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1721047102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PxlsHCfHsP0PabowsO6GN7c+uzAgObhIbcwJQODl+6Q=; b=uieIZwmEUXBtSD6DUpAVZoln3gMyZgPt0fesbRi1oNrl1AobI1xgU9qM33nOaWhXk7Fh8M ORFxTWDQzjdOn1vcdp+WgF0Mxd/CgZOiphAn82Xr+2Ufn8COqmVLQ0PuvgMJS3WRFkrgJR Fo7XGUvHHtUyS2LQOdmnmmav5E5N8AOnOWtjufoHPJn+JeiPND+I5064Aj54AWnz1WhSQa kYneJCZOtSTg92jbdDzROMyjfk5ry+ssfb+Tk0Qd53m17T4FWIwyrnA+5DGlOxCj3NOtJC As6V+a4LZfpsS8wbxhBVywZ8WVfUsUcATzmEljkE8YT7UV33SQK3U9666p6P0g== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1721047102; a=rsa-sha256; cv=none; b=aTjdp/OQt9c6LZ1iyIAFgIJLpWvNkiU+4dFyj155ZiESDwmHMkE1lBirIr9XMZDN5OhNjt MlN78Ul/cAz9K76Qc617nNLWmFgSKVc3HAN8uoUi38aiJ/32SLmMlru/X5AoPjBJok5gDZ Df/eT4VhkFsrZeuXuwHGKDgSt/40QkldLYwmYyFqgEyFn1zDqr0MZn+yBSflDWbKIepXAx dZM5pM8px7C81N+aVmOClKRtKM+2l0pyzi9YLoKJRarGJjlpZQkCRfW9KsNoeFuPjd27sK HEZBLt55n4QPXqyWJmUzymyd43tVNpEkOyWwzTankCbPAIk2McjO68TWfGoSFQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1721047102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PxlsHCfHsP0PabowsO6GN7c+uzAgObhIbcwJQODl+6Q=; b=kZwSaHmO/E3k83P8NpEtY7Ugq48Q6w8xnSpibDM/TswBAqLlLPKt3yL7mIPc/GKrhr02BB MIE6/NxgLm97seeWEKkTS/k6DxluTdjqTQZGcbPdxGNj5rl5gx1jbXnI7RgbxYonFJ2P61 AdXL+1KfPNCyp8/Xz7HMpUxi0nGwHXuWCqMShT1sYTuYJ+Qq+rDjtYBuN+hGxLmA2dZ/D+ TCUdf14Y/5Nbl1weZLW8dXltSW8ZqI7mS9n8SJy1pE0M+cFtlJmB15XN3hY9K5UHxH4Kgj 7TyqRRf3i8rgEAdGIs7IUX4ED0NPzQCAob6FboNXggyd2PCShgWAiMJMPpSFNQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4WN1vf52qRzt3G; Mon, 15 Jul 2024 12:38:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 46FCcM5t061032; Mon, 15 Jul 2024 12:38:22 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 46FCcMtJ061029; Mon, 15 Jul 2024 12:38:22 GMT (envelope-from git) Date: Mon, 15 Jul 2024 12:38:22 GMT Message-Id: <202407151238.46FCcMtJ061029@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: 98740a0ef56f - stable/14 - arm64: Use the UL macro in TCR_EL1 defines List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/14 X-Git-Reftype: branch X-Git-Commit: 98740a0ef56f6b3c5cc9226728ccbe56c2bf07ed Auto-Submitted: auto-generated The branch stable/14 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=98740a0ef56f6b3c5cc9226728ccbe56c2bf07ed commit 98740a0ef56f6b3c5cc9226728ccbe56c2bf07ed Author: Andrew Turner AuthorDate: 2024-05-22 08:18:39 +0000 Commit: Andrew Turner CommitDate: 2024-07-15 12:26:46 +0000 arm64: Use the UL macro in TCR_EL1 defines While clang can handle numbers with a UL suffix in assembly files gcc/gas is unable to. Switch to use the UL macro for TCR_EL1 defines as some are used in locore.S Reviewed by: brooks, jhb Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45261 (cherry picked from commit 29c1cf9860e531146220d9dc3596e4c79f91cfcd) --- sys/arm64/include/armreg.h | 96 +++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index e90c6a57fd55..243c9276cee0 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2133,99 +2133,99 @@ /* TCR_EL1 - Translation Control Register */ /* Bits 63:59 are reserved */ #define TCR_TCMA1_SHIFT 58 -#define TCR_TCMA1 (1UL << TCR_TCMA1_SHIFT) +#define TCR_TCMA1 (UL(1) << TCR_TCMA1_SHIFT) #define TCR_TCMA0_SHIFT 57 -#define TCR_TCMA0 (1UL << TCR_TCMA0_SHIFT) +#define TCR_TCMA0 (UL(1) << TCR_TCMA0_SHIFT) #define TCR_E0PD1_SHIFT 56 -#define TCR_E0PD1 (1UL << TCR_E0PD1_SHIFT) +#define TCR_E0PD1 (UL(1) << TCR_E0PD1_SHIFT) #define TCR_E0PD0_SHIFT 55 -#define TCR_E0PD0 (1UL << TCR_E0PD0_SHIFT) +#define TCR_E0PD0 (UL(1) << TCR_E0PD0_SHIFT) #define TCR_NFD1_SHIFT 54 -#define TCR_NFD1 (1UL << TCR_NFD1_SHIFT) +#define TCR_NFD1 (UL(1) << TCR_NFD1_SHIFT) #define TCR_NFD0_SHIFT 53 -#define TCR_NFD0 (1UL << TCR_NFD0_SHIFT) +#define TCR_NFD0 (UL(1) << TCR_NFD0_SHIFT) #define TCR_TBID1_SHIFT 52 -#define TCR_TBID1 (1UL << TCR_TBID1_SHIFT) +#define TCR_TBID1 (UL(1) << TCR_TBID1_SHIFT) #define TCR_TBID0_SHIFT 51 -#define TCR_TBID0 (1UL << TCR_TBID0_SHIFT) +#define TCR_TBID0 (UL(1) << TCR_TBID0_SHIFT) #define TCR_HWU162_SHIFT 50 -#define TCR_HWU162 (1UL << TCR_HWU162_SHIFT) +#define TCR_HWU162 (UL(1) << TCR_HWU162_SHIFT) #define TCR_HWU161_SHIFT 49 -#define TCR_HWU161 (1UL << TCR_HWU161_SHIFT) +#define TCR_HWU161 (UL(1) << TCR_HWU161_SHIFT) #define TCR_HWU160_SHIFT 48 -#define TCR_HWU160 (1UL << TCR_HWU160_SHIFT) +#define TCR_HWU160 (UL(1) << TCR_HWU160_SHIFT) #define TCR_HWU159_SHIFT 47 -#define TCR_HWU159 (1UL << TCR_HWU159_SHIFT) +#define TCR_HWU159 (UL(1) << TCR_HWU159_SHIFT) #define TCR_HWU1 \ (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) #define TCR_HWU062_SHIFT 46 -#define TCR_HWU062 (1UL << TCR_HWU062_SHIFT) +#define TCR_HWU062 (UL(1) << TCR_HWU062_SHIFT) #define TCR_HWU061_SHIFT 45 -#define TCR_HWU061 (1UL << TCR_HWU061_SHIFT) +#define TCR_HWU061 (UL(1) << TCR_HWU061_SHIFT) #define TCR_HWU060_SHIFT 44 -#define TCR_HWU060 (1UL << TCR_HWU060_SHIFT) +#define TCR_HWU060 (UL(1) << TCR_HWU060_SHIFT) #define TCR_HWU059_SHIFT 43 -#define TCR_HWU059 (1UL << TCR_HWU059_SHIFT) +#define TCR_HWU059 (UL(1) << TCR_HWU059_SHIFT) #define TCR_HWU0 \ (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) #define TCR_HPD1_SHIFT 42 -#define TCR_HPD1 (1UL << TCR_HPD1_SHIFT) +#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT) #define TCR_HPD0_SHIFT 41 -#define TCR_HPD0 (1UL << TCR_HPD0_SHIFT) +#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT) #define TCR_HD_SHIFT 40 -#define TCR_HD (1UL << TCR_HD_SHIFT) +#define TCR_HD (UL(1) << TCR_HD_SHIFT) #define TCR_HA_SHIFT 39 -#define TCR_HA (1UL << TCR_HA_SHIFT) +#define TCR_HA (UL(1) << TCR_HA_SHIFT) #define TCR_TBI1_SHIFT 38 -#define TCR_TBI1 (1UL << TCR_TBI1_SHIFT) +#define TCR_TBI1 (UL(1) << TCR_TBI1_SHIFT) #define TCR_TBI0_SHIFT 37 -#define TCR_TBI0 (1UL << TCR_TBI0_SHIFT) +#define TCR_TBI0 (UL(1) << TCR_TBI0_SHIFT) #define TCR_ASID_SHIFT 36 #define TCR_ASID_WIDTH 1 -#define TCR_ASID_16 (1UL << TCR_ASID_SHIFT) +#define TCR_ASID_16 (UL(1) << TCR_ASID_SHIFT) /* Bit 35 is reserved */ #define TCR_IPS_SHIFT 32 #define TCR_IPS_WIDTH 3 -#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) -#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) -#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) -#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) -#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) -#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) +#define TCR_IPS_32BIT (UL(0) << TCR_IPS_SHIFT) +#define TCR_IPS_36BIT (UL(1) << TCR_IPS_SHIFT) +#define TCR_IPS_40BIT (UL(2) << TCR_IPS_SHIFT) +#define TCR_IPS_42BIT (UL(3) << TCR_IPS_SHIFT) +#define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT) +#define TCR_IPS_48BIT (UL(5) << TCR_IPS_SHIFT) #define TCR_TG1_SHIFT 30 -#define TCR_TG1_MASK (3UL << TCR_TG1_SHIFT) -#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) -#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) -#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) +#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) +#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) +#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) +#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) #define TCR_SH1_SHIFT 28 -#define TCR_SH1_IS (3UL << TCR_SH1_SHIFT) +#define TCR_SH1_IS (UL(3) << TCR_SH1_SHIFT) #define TCR_ORGN1_SHIFT 26 -#define TCR_ORGN1_WBWA (1UL << TCR_ORGN1_SHIFT) +#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) #define TCR_IRGN1_SHIFT 24 -#define TCR_IRGN1_WBWA (1UL << TCR_IRGN1_SHIFT) +#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) #define TCR_EPD1_SHIFT 23 -#define TCR_EPD1 (1UL << TCR_EPD1_SHIFT) +#define TCR_EPD1 (UL(1) << TCR_EPD1_SHIFT) #define TCR_A1_SHIFT 22 -#define TCR_A1 (0x1UL << TCR_A1_SHIFT) +#define TCR_A1 (UL(1) << TCR_A1_SHIFT) #define TCR_T1SZ_SHIFT 16 -#define TCR_T1SZ_MASK (0x3fUL << TCR_T1SZ_SHIFT) +#define TCR_T1SZ_MASK (UL(0x3f) << TCR_T1SZ_SHIFT) #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) #define TCR_TG0_SHIFT 14 -#define TCR_TG0_MASK (3UL << TCR_TG0_SHIFT) -#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) -#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) -#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) +#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) +#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) +#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) +#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) #define TCR_SH0_SHIFT 12 -#define TCR_SH0_IS (3UL << TCR_SH0_SHIFT) +#define TCR_SH0_IS (UL(3) << TCR_SH0_SHIFT) #define TCR_ORGN0_SHIFT 10 -#define TCR_ORGN0_WBWA (1UL << TCR_ORGN0_SHIFT) +#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) #define TCR_IRGN0_SHIFT 8 -#define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) +#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) #define TCR_EPD0_SHIFT 7 -#define TCR_EPD0 (1UL << TCR_EPD0_SHIFT) +#define TCR_EPD0 (UL(1) << TCR_EPD0_SHIFT) /* Bit 6 is reserved */ #define TCR_T0SZ_SHIFT 0 -#define TCR_T0SZ_MASK (0x3fUL << TCR_T0SZ_SHIFT) +#define TCR_T0SZ_MASK (UL(0x3f) << TCR_T0SZ_SHIFT) #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))