git: 41b30bbc1a57 - main - uart: Add support for Brainboxes / Intashield serial cards.
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Date: Tue, 31 Dec 2024 09:06:22 UTC
The branch main has been updated by nyan:
URL: https://cgit.FreeBSD.org/src/commit/?id=41b30bbc1a57b60afee9acdd6ad240c92ef13790
commit 41b30bbc1a57b60afee9acdd6ad240c92ef13790
Author: Yoshihiro Takahashi <nyan@FreeBSD.org>
AuthorDate: 2024-12-31 09:04:27 +0000
Commit: Yoshihiro Takahashi <nyan@FreeBSD.org>
CommitDate: 2024-12-31 09:04:27 +0000
uart: Add support for Brainboxes / Intashield serial cards.
PR: 283226
Reported by: Cameron Williams
---
sys/dev/puc/pucdata.c | 422 ++++++++++++++++++++++++++++++++++++++++++++
sys/dev/uart/uart_bus_pci.c | 14 ++
2 files changed, 436 insertions(+)
diff --git a/sys/dev/puc/pucdata.c b/sys/dev/puc/pucdata.c
index f127e27e7b08..e911a407cca9 100644
--- a/sys/dev/puc/pucdata.c
+++ b/sys/dev/puc/pucdata.c
@@ -493,6 +493,428 @@ const struct puc_cfg puc_pci_devices[] = {
.config_function = puc_config_siig
},
+ { 0x135a, 0x0841, 0xffff, 0,
+ "Brainboxes UC-268",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0861, 0xffff, 0,
+ "Brainboxes UC-257",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0862, 0xffff, 0,
+ "Brainboxes UC-257",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0863, 0xffff, 0,
+ "Brainboxes UC-257",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0881, 0xffff, 0,
+ "Brainboxes UC-279",
+ DEFAULT_RCLK,
+ PUC_PORT_8S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08a1, 0xffff, 0,
+ "Brainboxes UC-313",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08a2, 0xffff, 0,
+ "Brainboxes UC-313",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08a3, 0xffff, 0,
+ "Brainboxes UC-313",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08c1, 0xffff, 0,
+ "Brainboxes UC-310",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08e1, 0xffff, 0,
+ "Brainboxes UC-302",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08e2, 0xffff, 0,
+ "Brainboxes UC-302",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x08e3, 0xffff, 0,
+ "Brainboxes UC-302",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0901, 0xffff, 0,
+ "Brainboxes UC-431",
+ DEFAULT_RCLK,
+ PUC_PORT_3S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0921, 0xffff, 0,
+ "Brainboxes UC-420",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0981, 0xffff, 0,
+ "Brainboxes UC-475",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0982, 0xffff, 0,
+ "Brainboxes UC-475",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x09a1, 0xffff, 0,
+ "Brainboxes UC-607",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x09a2, 0xffff, 0,
+ "Brainboxes UC-607",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x09a3, 0xffff, 0,
+ "Brainboxes UC-607",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0a81, 0xffff, 0,
+ "Brainboxes UC-357",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0a82, 0xffff, 0,
+ "Brainboxes UC-357",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0a83, 0xffff, 0,
+ "Brainboxes UC-357",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0ac1, 0xffff, 0,
+ "Brainboxes UP-189",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0ac2, 0xffff, 0,
+ "Brainboxes UP-189",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0ac3, 0xffff, 0,
+ "Brainboxes UP-189",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0b01, 0xffff, 0,
+ "Brainboxes UC-346",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0b02, 0xffff, 0,
+ "Brainboxes UC-346",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0b21, 0xffff, 0,
+ "Brainboxes UP-200",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0b22, 0xffff, 0,
+ "Brainboxes UP-200",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0b23, 0xffff, 0,
+ "Brainboxes UP-200",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0ba1, 0xffff, 0,
+ "Brainboxes UC-101",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0bc1, 0xffff, 0,
+ "Brainboxes UC-203",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0bc2, 0xffff, 0,
+ "Brainboxes UC-203",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c01, 0xffff, 0,
+ "Brainboxes UP-869",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c02, 0xffff, 0,
+ "Brainboxes UP-869",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c03, 0xffff, 0,
+ "Brainboxes UP-869",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c21, 0xffff, 0,
+ "Brainboxes UP-880",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c22, 0xffff, 0,
+ "Brainboxes UP-880",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c23, 0xffff, 0,
+ "Brainboxes UP-880",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0c41, 0xffff, 0,
+ "Brainboxes UC-368",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0ca1, 0xffff, 0,
+ "Brainboxes UC-253",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0d21, 0xffff, 0,
+ "Brainboxes UC-260",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0d41, 0xffff, 0,
+ "Brainboxes UC-836",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0d80, 0xffff, 0,
+ "Intashield IS-200",
+ DEFAULT_RCLK,
+ PUC_PORT_2S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0dc0, 0xffff, 0,
+ "Intashield IS-400",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0e41, 0xffff, 0,
+ "Brainboxes PX-279",
+ DEFAULT_RCLK,
+ PUC_PORT_8S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x0e61, 0xffff, 0,
+ "Brainboxes UC-414",
+ DEFAULT_RCLK,
+ PUC_PORT_4S, 0x18, 0, 8,
+ },
+
+ { 0x135a, 0x400a, 0xffff, 0,
+ "Brainboxes PX-260",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x400b, 0xffff, 0,
+ "Brainboxes PX-320",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x400c, 0xffff, 0,
+ "Brainboxes PX-313",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x400e, 0xffff, 0,
+ "Brainboxes PX-310",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x400f, 0xffff, 0,
+ "Brainboxes PX-346",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4010, 0xffff, 0,
+ "Brainboxes PX-368",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4011, 0xffff, 0,
+ "Brainboxes PX-420",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4012, 0xffff, 0,
+ "Brainboxes PX-431",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4013, 0xffff, 0,
+ "Brainboxes PX-820",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4014, 0xffff, 0,
+ "Brainboxes PX-831",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4015, 0xffff, 0,
+ "Brainboxes PX-257",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4016, 0xffff, 0,
+ "Brainboxes PX-246",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4017, 0xffff, 0,
+ "Brainboxes PX-846",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4018, 0xffff, 0,
+ "Brainboxes PX-857",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4019, 0xffff, 0,
+ "Brainboxes PX-101",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x401d, 0xffff, 0,
+ "Brainboxes PX-475",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x401e, 0xffff, 0,
+ "Brainboxes PX-803",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4027, 0xffff, 0,
+ "Intashield IX-100",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4028, 0xffff, 0,
+ "Intashield IX-200",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
+ { 0x135a, 0x4029, 0xffff, 0,
+ "Intashield IX-400",
+ DEFAULT_RCLK * 0x22,
+ PUC_PORT_NONSTANDARD, 0x10, 0, -1,
+ .config_function = puc_config_oxford_pcie
+ },
+
{ 0x135c, 0x0010, 0xffff, 0,
"Quatech QSC-100",
-3, /* max 8x clock rate */
diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c
index 5f82ef9307d0..14ac213066b8 100644
--- a/sys/dev/uart/uart_bus_pci.c
+++ b/sys/dev/uart/uart_bus_pci.c
@@ -106,6 +106,20 @@ static const struct pci_id pci_ns8250_ids[] = {
{ 0x131f, 0x2000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x10 },
{ 0x131f, 0x2001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x10 },
{ 0x131f, 0x2002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x10 },
+{ 0x135a, 0x0a61, 0xffff, 0, "Brainboxes UC-324", 0x18 },
+{ 0x135a, 0x0aa1, 0xffff, 0, "Brainboxes UC-246", 0x18 },
+{ 0x135a, 0x0aa2, 0xffff, 0, "Brainboxes UC-246", 0x18 },
+{ 0x135a, 0x0d60, 0xffff, 0, "Intashield IS-100", 0x18 },
+{ 0x135a, 0x0da0, 0xffff, 0, "Intashield IS-300", 0x18 },
+{ 0x135a, 0x4000, 0xffff, 0, "Brainboxes PX-420", 0x10 },
+{ 0x135a, 0x4001, 0xffff, 0, "Brainboxes PX-431", 0x10 },
+{ 0x135a, 0x4002, 0xffff, 0, "Brainboxes PX-820", 0x10 },
+{ 0x135a, 0x4003, 0xffff, 0, "Brainboxes PX-831", 0x10 },
+{ 0x135a, 0x4004, 0xffff, 0, "Brainboxes PX-246", 0x10 },
+{ 0x135a, 0x4005, 0xffff, 0, "Brainboxes PX-101", 0x10 },
+{ 0x135a, 0x4006, 0xffff, 0, "Brainboxes PX-257", 0x10 },
+{ 0x135a, 0x4008, 0xffff, 0, "Brainboxes PX-846", 0x10 },
+{ 0x135a, 0x4009, 0xffff, 0, "Brainboxes PX-857", 0x10 },
{ 0x135c, 0x0190, 0xffff, 0, "Quatech SSCLP-100", 0x18 },
{ 0x135c, 0x01c0, 0xffff, 0, "Quatech SSCLP-200/300", 0x18 },
{ 0x135e, 0x7101, 0xffff, 0, "Sealevel Systems Single Port RS-232/422/485/530",