From nobody Tue Dec 17 11:28:49 2024 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4YCF1s2QSRz5h5hK; Tue, 17 Dec 2024 11:28:49 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4YCF1s1v1Tz4VF0; Tue, 17 Dec 2024 11:28:49 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1734434929; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=X8T5XX6XIz5575M+bAxW8z+ADhX3+YWwgewqsvUctfA=; b=GoCOORLS47B+e6UeZ7l0NId23Vrq4FIjO/YO9I+YRe3Kt1/sg9cDWhxdkmkiRJsxWSUUD4 q9HAITerioyxJWfivtDQeRmI8l1RhlrB33igBekvnnX2Xs5dtb+DlL4cvKBg8h83PgBsbe wWMyRtPtPR9Xd4r2u3ZD1oGWY6jZFfqzLd2ulKM8++YdEQf4d8DXs60Dr/Cww5jbFaMROr HblsTM8yKD9lrmFfUaVjA3qWNRFS7rFMFn9SKfU0czs0d3A14ZqpZoAjJe+6udEf+jW7hM zYxZcGFzqnDFwIRuSrPK/9hasEGa0UqDX7S3+pnp1OIwwEecoeYqf7kQTNxcXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1734434929; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=X8T5XX6XIz5575M+bAxW8z+ADhX3+YWwgewqsvUctfA=; b=pUWpc/PAG/egzudhNlGXpFfOSGwgdkIklmhBH+mmb9Pe0P50k15tYxAJA4Ogb7XDFeXaWk 0IyY4Y4YUUQ9bU8zZ+e0TXqMNqfbVEwd39N9XFISKgEF1bG683BOFSFdsjEveg0yAQfBEh LZWKkUBAus7qHikKZ228CG7xllfd6wHNC1daw2Fs4wSlFPQs9QzQiTEkp6U+GH4q1sc8vc wri6ERz3m1XAvERBv82crdDWjvA1GHR6ufooXiz3O0RecZkxM0dleBv2X0xqbRx2N2mH1F GxmGWgMmFlaZqy+mciks48SxlCQVhDMFFS/JuU8q7Xpp73eADofEwx6dFlixsQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1734434929; a=rsa-sha256; cv=none; b=X8cYPu3AASpXs1/YdD8G1J+rreSQoXgvHtWWx8J2Xd9FSRRDGD9JViJaOlW7srPocAzuzq 0z80moDge8AtF2Qo4DWTF7jGlgho5z06NcRrzpKUY6Wms5UVKPhrddiBWO7QszVy37oBzW RCW3ZFEg3GT1fASvKXnuaqFB+axVhk+5LrDS+LDle4B6wDNpllyWRsGJ4KmZzi7x2XbgFr qqXbcC9KHQt/21+jNUZHphuPVCNKqn5whF3cfKD8wgmsSzZVrkbqWAoxUvntxAMwUNJsB0 WG67CJ3sn/YBivBxc2vLrcXYb9hChMw9nmMmEetPS9P9mQEx2etxvuJDPzLvXg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4YCF1s1VDwzLnc; Tue, 17 Dec 2024 11:28:49 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 4BHBSn6N073706; Tue, 17 Dec 2024 11:28:49 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 4BHBSn0S073703; Tue, 17 Dec 2024 11:28:49 GMT (envelope-from git) Date: Tue, 17 Dec 2024 11:28:49 GMT Message-Id: <202412171128.4BHBSn0S073703@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Ruslan Bukin Subject: git: 6766e8ceb5c6 - main - riscv: Add SiFive CCache driver. List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: br X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 6766e8ceb5c6bc27453b45a21330aaf59c783fd5 Auto-Submitted: auto-generated The branch main has been updated by br: URL: https://cgit.FreeBSD.org/src/commit/?id=6766e8ceb5c6bc27453b45a21330aaf59c783fd5 commit 6766e8ceb5c6bc27453b45a21330aaf59c783fd5 Author: Ruslan Bukin AuthorDate: 2024-12-17 11:21:22 +0000 Commit: Ruslan Bukin CommitDate: 2024-12-17 11:28:25 +0000 riscv: Add SiFive CCache driver. Eswin EIC7700 has non-coherent DMAs but predate the standard RISC-V Zicbom extension, so we need to use the SiFive CCache controller for non-standard cache management operations. Tested on SiFive Premier P550. Reviewed by: mhorne, jrtc27 Differential Revision: https://reviews.freebsd.org/D47831 --- sys/riscv/sifive/sifive_ccache.c | 177 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/sys/riscv/sifive/sifive_ccache.c b/sys/riscv/sifive/sifive_ccache.c new file mode 100644 index 000000000000..9006d02aa85e --- /dev/null +++ b/sys/riscv/sifive/sifive_ccache.c @@ -0,0 +1,177 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 Ruslan Bukin + * + * This software was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under Innovate + * UK project 105694, "Digital Security by Design (DSbD) Technology Platform + * Prototype". + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#define SIFIVE_CCACHE_CONFIG 0x000 +#define CCACHE_CONFIG_WAYS_S 8 +#define CCACHE_CONFIG_WAYS_M (0xff << CCACHE_CONFIG_WAYS_S) +#define SIFIVE_CCACHE_WAYENABLE 0x008 +#define SIFIVE_CCACHE_FLUSH64 0x200 + +#define SIFIVE_CCACHE_LINE_SIZE 64 + +#define RD8(sc, off) (bus_read_8((sc)->res, (off))) +#define WR8(sc, off, val) (bus_write_8((sc)->res, (off), (val))) +#define CC_WR8(offset, value) \ + *(volatile uint64_t *)((uintptr_t)ccache_va + (offset)) = (value) + +static struct ofw_compat_data compat_data[] = { + { "sifive,eic7700", 1 }, + { NULL, 0 } +}; + +struct ccache_softc { + struct resource *res; +}; + +static void *ccache_va = NULL; + +static struct resource_spec ccache_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +/* + * Non-standard EIC7700 cache-flushing routine. + */ +static void +ccache_flush_range(vm_offset_t start, size_t len) +{ + vm_offset_t paddr; + vm_offset_t sva; + vm_offset_t step; + uint64_t line; + + if (ccache_va == NULL || len == 0) + return; + + mb(); + + for (sva = start; len > 0;) { + paddr = pmap_kextract(sva); + step = min(PAGE_SIZE - (paddr & PAGE_MASK), len); + for (line = rounddown2(paddr, SIFIVE_CCACHE_LINE_SIZE); + line < paddr + step; + line += SIFIVE_CCACHE_LINE_SIZE) + CC_WR8(SIFIVE_CCACHE_FLUSH64, line); + sva += step; + len -= step; + } + + mb(); +} + +static void +ccache_install_hooks(void) +{ + struct riscv_cache_ops eswin_ops; + + eswin_ops.dcache_wbinv_range = ccache_flush_range; + eswin_ops.dcache_inv_range = ccache_flush_range; + eswin_ops.dcache_wb_range = ccache_flush_range; + + riscv_cache_install_hooks(&eswin_ops, SIFIVE_CCACHE_LINE_SIZE); +} + +static int +ccache_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + if (device_get_unit(dev) != 0) + return (ENXIO); + + device_set_desc(dev, "SiFive Cache Controller"); + + return (BUS_PROBE_DEFAULT); +} + +static int +ccache_attach(device_t dev) +{ + struct ccache_softc *sc; + size_t config, ways; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, ccache_spec, &sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + return (ENXIO); + } + + /* Non-standard EIC7700 cache unit configuration. */ + config = RD8(sc, SIFIVE_CCACHE_CONFIG); + ways = (config & CCACHE_CONFIG_WAYS_M) >> CCACHE_CONFIG_WAYS_S; + WR8(sc, SIFIVE_CCACHE_WAYENABLE, (ways - 1)); + + ccache_va = rman_get_virtual(sc->res); + ccache_install_hooks(); + + return (0); +} + +static device_method_t ccache_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, ccache_probe), + DEVMETHOD(device_attach, ccache_attach), + DEVMETHOD_END +}; + +static driver_t ccache_driver = { + "ccache", + ccache_methods, + sizeof(struct ccache_softc), +}; + +EARLY_DRIVER_MODULE(ccache, simplebus, ccache_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_FIRST); +MODULE_VERSION(ccache, 1);