From nobody Fri Jul 28 12:08:01 2023 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RC5xY6j7qz4pyQ2; Fri, 28 Jul 2023 12:08:01 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RC5xY56F0z42dC; Fri, 28 Jul 2023 12:08:01 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1690546081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=x7a35wjof0+ZW72xVOMECIsTGb7J7oROyK+W3PpcyBo=; b=VCjTUsaLKGIrpDF8iD0W0IM9X2t8WAxsYyWpRM/z34Vb1GsphXn2yqmGPwPxCERDXkneCE xYXdhZxB3f4j4PELVwmpIn0Pu8+bVcI76RROQh9fzHNT3Yhr2DfpNTF2uszYyc/oVIfhAE li7ZgznNNXBj1nKuvNK5QJJ54hlOGengo3I2V39fQTy0xts9mF+B1xTAzSxIgsDiZKKfvd gI9MhJAaFDiYYzyU9Reeidce4t4dCU70OUGe5jXAnAObN39RWDkhkrRsWKBjHJh09dKXay wuxfqur6JgZWlMXPrTa1qpvnoqIFeW/ZHNliSpv4mGe2jiqTSwwYy3BewjQ2HQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1690546081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=x7a35wjof0+ZW72xVOMECIsTGb7J7oROyK+W3PpcyBo=; b=xYh/bSf6PSO1kB6JeRrI5qzE8HFlFm9eKM9xikX/7f1aRPD/zIpNwMT2d+7Nco+APU9qaO JM/sfaPhd2pmGVRSz+hUHZnvZ37WjZC2XfiM6qXmufWJXFUikByR3igRJtCkXkujKJujxU fMVzV4/w1HEr4Teky1L5M03BrNGEmzvIdJT+Y4Q41rFxdEcbTf+rcx5ouh4ESu8cj16AxI dS8SQ6Q9k8DJfPdSaP7cEfCni9a6Y6SMqtCbbzQwGZ+nGIOO2QxWe9UFRWqP2PzDtShgv+ cOw5q4Wdjt6SVYpq3xko1HnhR7ZISmnG+7DelugwEhsrADeITHydcgFd9Q6G8A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1690546081; a=rsa-sha256; cv=none; b=nZW/9zslDRjd4HDd698TUJZlOm3X4LN+TB/NNUXQcueAwUno+H9c0yHxW9ua3jKqxDIIvA KufT7cpCzb9KFhnSIx8u1ROaYQ5tt15YulHPnWWQsT3oqaIonYbo8F77tS6TVcg4rHgTQ9 rfox3g7Ufb1g9gRlJ9L4+KOU50oswxUp2FTPtNAOTUgBJZNoynN6F88SjfrB4EAhXKNpnv FkcOxvjVO+IEKv1ot9blloElqI2FtbUiq/VM93Bvh2uNBNsDhIH2bgOYHtqGOdkTnefKK6 jBETmratXbiFBiofHeSQZoSYICX5QXQMfjokockv7Qg3+OL0i5K7e2qYwx5/lg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4RC5xY3zWFzqr4; Fri, 28 Jul 2023 12:08:01 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 36SC81qg062066; Fri, 28 Jul 2023 12:08:01 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 36SC81pa062065; Fri, 28 Jul 2023 12:08:01 GMT (envelope-from git) Date: Fri, 28 Jul 2023 12:08:01 GMT Message-Id: <202307281208.36SC81pa062065@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: de01309926e2 - main - arm64: Update the ID_AA64ISAR1_EL1 fields List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: de01309926e21e1cff196b6b23cff6c52064aa0e Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=de01309926e21e1cff196b6b23cff6c52064aa0e commit de01309926e21e1cff196b6b23cff6c52064aa0e Author: Andrew Turner AuthorDate: 2023-07-06 10:01:11 +0000 Commit: Andrew Turner CommitDate: 2023-07-28 11:53:01 +0000 arm64: Update the ID_AA64ISAR1_EL1 fields While here move to decimal for the _op and _CR definitions to be used by a future macro to define the register when the assembler doesn't know about it. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40889 --- sys/arm64/arm64/identcpu.c | 15 +++++++++++++++ sys/arm64/include/armreg.h | 23 ++++++++++++++++++----- 2 files changed, 33 insertions(+), 5 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index af5914034db4..48c5cf44a9b5 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -665,6 +665,18 @@ static const struct mrs_field id_aa64isar0_fields[] = { /* ID_AA64ISAR1_EL1 */ +static const struct mrs_field_value id_aa64isar1_ls64[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LS64, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_V, "LS64v"), + MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_ACCDATA, "LS64+ACCDATA"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64isar1_xs[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, XS, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64isar1_i8mm[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL), MRS_FIELD_VALUE_END, @@ -687,6 +699,7 @@ static const struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = { static const struct mrs_field_value id_aa64isar1_bf16[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64ISAR1_BF16_EBF, "EBF16"), MRS_FIELD_VALUE_END, }; @@ -820,6 +833,8 @@ static const struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = { }; static const struct mrs_field id_aa64isar1_fields[] = { + MRS_FIELD(ID_AA64ISAR1, LS64, false, MRS_EXACT, id_aa64isar1_ls64), + MRS_FIELD(ID_AA64ISAR1, XS, false, MRS_EXACT, id_aa64isar1_xs), MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps), MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh, diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 3610a59834b1..6ada3649042f 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -656,11 +656,11 @@ /* ID_AA64ISAR1_EL1 */ #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) -#define ID_AA64ISAR1_EL1_op0 0x3 -#define ID_AA64ISAR1_EL1_op1 0x0 -#define ID_AA64ISAR1_EL1_CRn 0x0 -#define ID_AA64ISAR1_EL1_CRm 0x6 -#define ID_AA64ISAR1_EL1_op2 0x1 +#define ID_AA64ISAR1_EL1_op0 3 +#define ID_AA64ISAR1_EL1_op1 0 +#define ID_AA64ISAR1_EL1_CRn 0 +#define ID_AA64ISAR1_EL1_CRm 6 +#define ID_AA64ISAR1_EL1_op2 1 #define ID_AA64ISAR1_DPB_SHIFT 0 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) @@ -731,6 +731,7 @@ #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) +#define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_DGH_SHIFT 48 #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) @@ -741,6 +742,18 @@ #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) +#define ID_AA64ISAR1_XS_SHIFT 56 +#define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT) +#define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) +#define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT) +#define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT) +#define ID_AA64ISAR1_LS64_SHIFT 60 +#define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) +#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT) /* ID_AA64ISAR2_EL1 */ #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1)