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[131.111.5.143]) by smtp.gmail.com with ESMTPSA id hu29-20020a05600ca29d00b003db0f4e12c8sm2704739wmb.34.2023.01.18.13.10.50 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Jan 2023 13:10:51 -0800 (PST) Content-Type: text/plain; charset=us-ascii List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3696.120.41.1.1\)) Subject: Re: git: fd5e9210598c - main - Add CPU Ident for Qualcomm Kryo 400 (used in MS Dev Kit) From: Jessica Clarke In-Reply-To: <202301182105.30IL5fig040365@gitrepo.freebsd.org> Date: Wed, 18 Jan 2023 21:10:50 +0000 Cc: "src-committers@freebsd.org" , "dev-commits-src-all@freebsd.org" , "dev-commits-src-main@freebsd.org" Content-Transfer-Encoding: quoted-printable Message-Id: <85B5BFC4-C076-4959-B214-1ECA1975CA6D@freebsd.org> References: <202301182105.30IL5fig040365@gitrepo.freebsd.org> To: Allan Jude X-Mailer: Apple Mail (2.3696.120.41.1.1) X-Rspamd-Queue-Id: 4Nxz252kfbz43VY X-Spamd-Bar: ---- X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:15169, ipnet:209.85.128.0/17, country:US] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-ThisMailContainsUnwantedMimeParts: N On 18 Jan 2023, at 21:05, Allan Jude wrote: >=20 > The branch main has been updated by allanjude: >=20 > URL: = https://cgit.FreeBSD.org/src/commit/?id=3Dfd5e9210598cfafbecc05b5ec03da254= 83833f90 >=20 > commit fd5e9210598cfafbecc05b5ec03da25483833f90 > Author: Allan Jude > AuthorDate: 2022-12-20 21:31:38 +0000 > Commit: Allan Jude > CommitDate: 2023-01-18 21:04:49 +0000 >=20 > Add CPU Ident for Qualcomm Kryo 400 (used in MS Dev Kit) >=20 > Reviewed by: imp > Sponsored by: Klara, Inc. > Differential Revision: https://reviews.freebsd.org/D37767 > --- > sys/arm64/arm64/identcpu.c | 10 +++++++++- > sys/arm64/include/cpu.h | 5 +++++ > 2 files changed, 14 insertions(+), 1 deletion(-) >=20 > diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c > index 4f176ceef0b8..dadb589e9294 100644 > --- a/sys/arm64/arm64/identcpu.c > +++ b/sys/arm64/arm64/identcpu.c > @@ -199,6 +199,7 @@ static const struct cpu_parts cpu_parts_arm[] =3D = { > { CPU_PART_NEOVERSE_N1, "Neoverse-N1" }, > { CPU_PART_NEOVERSE_N2, "Neoverse-N2" }, > { CPU_PART_NEOVERSE_V1, "Neoverse-V1" }, > + { CPU_PART_NEOVERSE_V2, "Neoverse-V2" }, This (and the #define) isn't for a Qualcomm core... Jess > CPU_PART_NONE, > }; >=20 > @@ -215,6 +216,13 @@ static const struct cpu_parts cpu_parts_apm[] =3D = { > CPU_PART_NONE, > }; >=20 > +/* Qualcomm */ > +static const struct cpu_parts cpu_parts_qcom[] =3D { > + { CPU_PART_KRYO400_GOLD, "Kryo 400 Gold" }, > + { CPU_PART_KRYO400_SILVER, "Kryo 400 Silver" }, > + CPU_PART_NONE, > +}; > + > /* Unknown */ > static const struct cpu_parts cpu_parts_none[] =3D { > CPU_PART_NONE, > @@ -237,7 +245,7 @@ const struct cpu_implementers cpu_implementers[] =3D= { > { CPU_IMPL_INTEL, "Intel", cpu_parts_none }, > { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none }, > { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none }, > - { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_none }, > + { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_qcom }, > CPU_IMPLEMENTER_NONE, > }; >=20 > diff --git a/sys/arm64/include/cpu.h b/sys/arm64/include/cpu.h > index 2318c9d54cf3..280a759a4f06 100644 > --- a/sys/arm64/include/cpu.h > +++ b/sys/arm64/include/cpu.h > @@ -111,6 +111,7 @@ > #define CPU_PART_CORTEX_X1C 0xD4C > #define CPU_PART_CORTEX_A715 0xD4D > #define CPU_PART_CORTEX_X3 0xD4E > +#define CPU_PART_NEOVERSE_V2 0xD4F >=20 > /* Cavium Part numbers */ > #define CPU_PART_THUNDERX 0x0A1 > @@ -126,6 +127,10 @@ > /* APM / Ampere Part Number */ > #define CPU_PART_EMAG8180 0x000 >=20 > +/* Qualcomm */ > +#define CPU_PART_KRYO400_GOLD 0x804 > +#define CPU_PART_KRYO400_SILVER 0x805 > + > #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) > #define CPU_PART(midr) (((midr) >> 4) & 0xfff) > #define CPU_VAR(midr) (((midr) >> 20) & 0xf)