From nobody Tue Apr 04 02:51:48 2023 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4PrC2r6bctz43kSk; Tue, 4 Apr 2023 02:51:48 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4PrC2r69Mnz45vp; Tue, 4 Apr 2023 02:51:48 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1680576708; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=AT9VYbOcYvc4fFFjvKg6AdqxxJmffZqqhO8uofRXp/U=; b=iNDR8F1dxbGIOz1cx9kcixofknHqfSrVJ6ftuJdiuYuF3X1i7Cmpvkd/LuCmuGvJfrCytP dHzGiCeEubYS6Y2A/S3OO/g2HOv+FGRPr9F7NmVeNOGUNQEfYmkWykJ623juOA0gsvRh6P x76nkvfJz2NhiFFo6dP8aVkcW7mpyFlrDDWWszA1OFUv9qolRltVKQL9tZIFUBBdUCKD1D CwScLtDkipcPSw7IrUwQI8/FIAm1Ir1iGpCjcouc+XlB4uxywX58Xx12hAse788wF2wfGN 7gNjYeNcQ9I9Raneq2Ye7Ep73MfkBzoMqet/7h0Yd+d4xnOlWFBZ/GOj1o5KNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1680576708; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=AT9VYbOcYvc4fFFjvKg6AdqxxJmffZqqhO8uofRXp/U=; b=rovUuewU/fv1NAut5ybwV3ZjjqTLdq2BxqgP8emzJwZk+QUw2p1r5iXfkjVkqeUmcprLtd P75ZZtZjmRJcPsC9k7YKz6JwJ6c8MCc7DdtJdm2F+MkEca7jj5VUOT0xtkfJBUMl06AVlA waFTMYbHMzw0X7OrgCem/2aEq/sNNE+knYEeyw8pOK4djZI5d2LqYGNNI0RCe1SJWDN5v2 plq93dBsSRWSeJH6o5i+HySml+Of5D0vjvSs5/tLFiGgG6of5HHQ75mSd9rz5RpyOF1bDk AMO7IUWJttx6BXyxI3tMylp7KzTuHEOkmsnGmjUCbcHQDC/1nh1LWu7dGUyq3A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1680576708; a=rsa-sha256; cv=none; b=roKR8iuo9tkYLRvB7/Jq2w65Rgr1qLf2PyzUmCaneUgGWWJJjYrG8IOBwgF1u8Px5qSdcD E2M36fxHN2FL/GKoDEIQOhhswSiv6Pvsj+HIgTSsNoW2vJGkehJjYNqm/6ORUCbzAY+0Ik Kbb6ejNrJhz1r66bG3BRHagzPHnpCdPZcZRjnwgqKH+DkmuyHZ1KJP630jf2ls00lbdM12 MufRlIsH33D9dSzlB5S1c3s49EUHk1VlrJYTeErN+FSD0qkT5YrIIH9bB80UJIKkW//7qc lsXma3e8tDm0xkwVRpovLrY+qEjsLPfM8HBl5Hfwot2FC3Rs04zWvCdyKcgdBA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4PrC2r5F7kzNh0; Tue, 4 Apr 2023 02:51:48 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 3342pmSf062079; Tue, 4 Apr 2023 02:51:48 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 3342pmtG062078; Tue, 4 Apr 2023 02:51:48 GMT (envelope-from git) Date: Tue, 4 Apr 2023 02:51:48 GMT Message-Id: <202304040251.3342pmtG062078@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Ganbold Tsagaankhuu Subject: git: 396b6914c91f - main - Fix pcie phy enabling codes for RK3568 SoC. List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: ganbold X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 396b6914c91fcc1879f219715f126a8e8ab824d1 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by ganbold: URL: https://cgit.FreeBSD.org/src/commit/?id=396b6914c91fcc1879f219715f126a8e8ab824d1 commit 396b6914c91fcc1879f219715f126a8e8ab824d1 Author: Ganbold Tsagaankhuu AuthorDate: 2023-04-04 02:50:29 +0000 Commit: Ganbold Tsagaankhuu CommitDate: 2023-04-04 02:50:29 +0000 Fix pcie phy enabling codes for RK3568 SoC. Handle data-lanes property for pcie phy and set it accordingly. This makes devices attached to pcie3 work properly. For some RK3568 based boards, RTL8125B based device is connected it. So with this, realtek-re-kmod driver attaches and works. Partially obtained from OpenBSD. Tested on NanoPI-R5S, FireFly Station P2 boards. --- sys/arm64/rockchip/rk3568_pciephy.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/sys/arm64/rockchip/rk3568_pciephy.c b/sys/arm64/rockchip/rk3568_pciephy.c index 8a3f8067f228..5320f30e31bd 100644 --- a/sys/arm64/rockchip/rk3568_pciephy.c +++ b/sys/arm64/rockchip/rk3568_pciephy.c @@ -54,9 +54,8 @@ #define GRF_PCIE30PHY_CON1 0x04 #define GRF_PCIE30PHY_CON4 0x10 +#define GRF_PCIE30PHY_CON5 0x14 #define GRF_PCIE30PHY_CON6 0x18 -#define GRF_BIFURCATION_LANE_0_1 (1 << 0) -#define GRF_BIFURCATION_LANE_2_3 (1 << 1) #define GRF_PCIE30PHY_WR_EN (0xf << 16) #define GRF_PCIE30PHY_CON9 0x24 #define GRF_PCIE30PHY_DA_OCM ((1 << 15) | (1 << (15 + 16))) @@ -87,6 +86,7 @@ rk3568_pciephy_enable(struct phynode *phynode, bool enable) { device_t dev = phynode_get_device(phynode); struct rk3568_pciephy_softc *sc = device_get_softc(dev); + uint32_t data_lanes[2] = { 0, 0 }; int count; if (enable) { @@ -95,15 +95,30 @@ rk3568_pciephy_enable(struct phynode *phynode, bool enable) GRF_PCIE30PHY_DA_OCM); /* Set bifurcation according to DT entry */ - if (OF_hasprop(sc->node, "rockchip,bifurcation")) { + if (OF_hasprop(sc->node, "data-lanes")) { + OF_getencprop(sc->node, "data-lanes", data_lanes, + sizeof(data_lanes)); + if (data_lanes[0] > 0) { + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON5, + GRF_PCIE30PHY_WR_EN | (data_lanes[0] - 1)); + device_printf(dev, "pcie3x1 1 lane\n"); + } + if (data_lanes[1] > 0) { + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6, + GRF_PCIE30PHY_WR_EN | (data_lanes[1] - 1)); + device_printf(dev, "pcie3x2 1 lane\n"); + } + if (data_lanes[0] > 1 || data_lanes[1] > 1) + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1, + GRF_PCIE30PHY_DA_OCM); + + } else { + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON5, + GRF_PCIE30PHY_WR_EN); SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6, - GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_0_1); - SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1, - GRF_PCIE30PHY_DA_OCM); - device_printf(dev, "setup 2 x PCIeX1\n"); + GRF_PCIE30PHY_WR_EN); + device_printf(dev, "pcie3 2 lanes\n"); } - else - device_printf(dev, "setup 1 x PCIeX2\n"); hwreset_deassert(sc->phy_reset);