git: 9b4cbaa9c3da - main - riscv: handle misaligned address exceptions

The branch main has been updated by mhorne:

URL: https://cgit.FreeBSD.org/src/commit/?id=9b4cbaa9c3da233cf06381c3d22e3472ee586585

commit 9b4cbaa9c3da233cf06381c3d22e3472ee586585
Author:     Mitchell Horne <mhorne@FreeBSD.org>
AuthorDate: 2022-10-11 13:39:50 +0000
Commit:     Mitchell Horne <mhorne@FreeBSD.org>
CommitDate: 2022-10-11 13:39:50 +0000

    riscv: handle misaligned address exceptions
    
    If this exception is coming from userspace, send the appropriate SIGBUS
    to the process. If it's coming from the kernel this is still fatal, but
    we can give a better panic message.
    
    Typical misaligned loads/stores are emulated by the SBI firmware, and
    require no intervention from our kernel. The notable exception here is
    misaligned access with atomic instructions. These can generate the
    exception and panic seen in the PR.
    
    With this, we now handle all defined exception types.
    
    PR:             266109
    MFC after:      1 week
    Found by:       syzkaller
    Reported by:    P1umer <p1umer1337@gmail.com>
    Differential Revision:  https://reviews.freebsd.org/D36876
---
 sys/riscv/riscv/trap.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/sys/riscv/riscv/trap.c b/sys/riscv/riscv/trap.c
index 8b709b2de121..39e0fbb1d5bd 100644
--- a/sys/riscv/riscv/trap.c
+++ b/sys/riscv/riscv/trap.c
@@ -303,6 +303,13 @@ do_trap_supervisor(struct trapframe *frame)
 		dump_regs(frame);
 		panic("Memory access exception at 0x%016lx\n", frame->tf_sepc);
 		break;
+	case SCAUSE_LOAD_MISALIGNED:
+	case SCAUSE_STORE_MISALIGNED:
+	case SCAUSE_INST_MISALIGNED:
+		dump_regs(frame);
+		panic("Misaligned address exception at %#016lx: %#016lx\n",
+		    frame->tf_sepc, frame->tf_stval);
+		break;
 	case SCAUSE_STORE_PAGE_FAULT:
 	case SCAUSE_LOAD_PAGE_FAULT:
 	case SCAUSE_INST_PAGE_FAULT:
@@ -371,6 +378,13 @@ do_trap_user(struct trapframe *frame)
 		    exception);
 		userret(td, frame);
 		break;
+	case SCAUSE_LOAD_MISALIGNED:
+	case SCAUSE_STORE_MISALIGNED:
+	case SCAUSE_INST_MISALIGNED:
+		call_trapsignal(td, SIGBUS, BUS_ADRALN, (void *)frame->tf_sepc,
+		    exception);
+		userret(td, frame);
+		break;
 	case SCAUSE_STORE_PAGE_FAULT:
 	case SCAUSE_LOAD_PAGE_FAULT:
 	case SCAUSE_INST_PAGE_FAULT: