From nobody Tue May 31 03:25:35 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 3D8561B4556D; Tue, 31 May 2022 03:25:36 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4LByN014S6z3lVg; Tue, 31 May 2022 03:25:36 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1653967536; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=g8dFTIqrO11741rlRqoWD/oVvLMVYrps2GUnCAAghrw=; b=PyGEOeklUqyv+LjvyG9MN5XfwOU7okZWJT6AA822Jrtl/V4QPOFa5BttDpMN4yWDV3bdfx ANA3Hualx28cSTJEOuKOqlqgZHLdyH2JmiVeX6J6z6Wa6DGPL6DNQW5rnCcntxvJkmGlMr dKk3x/J+AU2RAt8p8CmaN7IyhE8Kbrp5YbIfJC7drxnALmWaN7l503ItIzwZQulDN/dSMj PZ7vKW7vHsok8SO6dXovubMnUJXQBIIIYK/Oi0mt7/TwZyQgNFLPNXH1ZSouT1g4Og8HBA pnJP7VrMY3GmXhDdyfOJ4+23aSYS7JbK4YoRBs9Yeo2dnon/acqtNS9EZYkWQw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 04FC323C62; Tue, 31 May 2022 03:25:36 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 24V3PZ1N004618; Tue, 31 May 2022 03:25:35 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 24V3PZYS004617; Tue, 31 May 2022 03:25:35 GMT (envelope-from git) Date: Tue, 31 May 2022 03:25:35 GMT Message-Id: <202205310325.24V3PZYS004617@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Alexander Motin Subject: git: fe109d311316 - main - hwpmc: Add basic Intel Alderlake CPUs support. List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mav X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: fe109d3113166c8e3b8557f0569c4e5a3597ac93 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1653967536; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=g8dFTIqrO11741rlRqoWD/oVvLMVYrps2GUnCAAghrw=; b=fbHWYia2FQ929UFwg0+eg8ZXYEo1FZv3GpCg9sXLGReQrro8qx7EvvvNGfHs5GsdsnSZ1e /Uh1mGr/VYS7JeAv4tYR8VuwVhJGkkC1A7cwqQQCrOQ6J0BjvlJxsIP088RdzOKZ3HdWzt GqS3hGivSBjfZwCVsrnm05+v24yJ+GxUToo/qhFX1KCkqD81jQikhVn0vqjJHm/w8z/omx ywWO/PN/JOTFaPSvh50DTh4r4hnEjZ6ou1ESH36gN3nUKI0OZz+mBcm5fBdfgTV4hzfUdz +0UzkbzbrVDaqQSWkIHKP2io2o4/V5JWZL735Z6lnlTvKFCYs4d8hl00OPb0Hg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1653967536; a=rsa-sha256; cv=none; b=NvTVOXC1w/8XaE2v1bG6oFawHFNepltNO42RXIUyoo/gF+DBkvCSsZuN06sAIlGUfYf/3n Z12QxMd0a2hOUF55PrQIliuk48sjiSpDyUiTBHKzSsBBmbgc7WDBw+hDIlaA+sLeUUaU0x 6rSO02J5xOhIdamnflnhfMuVLFwvs9aU+hmRF/hU3uGpIgQdsTleZA2H6mqG6LcIIOeLap JTA8SoJ9qiZjUVKnLr92yePXkUssrYA5mddBhBfDSKRukkE16cqgbrj+5XEzFnoyveivFh xXA5pDdvtnFNOis+Wl1xYsZUjG6egIDc+imjS3sVpZoteyDyisLvUL1cKRDG2g== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=fe109d3113166c8e3b8557f0569c4e5a3597ac93 commit fe109d3113166c8e3b8557f0569c4e5a3597ac93 Author: Alexander Motin AuthorDate: 2022-05-31 03:17:37 +0000 Commit: Alexander Motin CommitDate: 2022-05-31 03:17:37 +0000 hwpmc: Add basic Intel Alderlake CPUs support. The PMC subsystem is not designed for non-uniform CPU capabilities (P/E-cores are different), but at least several working architectural events like cpu_clk_unhalted.thread_p should be better than nothing. MFC after: 1 month --- sys/dev/hwpmc/hwpmc_core.c | 1 + sys/dev/hwpmc/hwpmc_intel.c | 107 +++++++++++--------------------------------- sys/sys/pmc.h | 1 + 3 files changed, 29 insertions(+), 80 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index 043ca95a305f..1b3c59163141 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -781,6 +781,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, case PMC_CPU_INTEL_SKYLAKE_XEON: case PMC_CPU_INTEL_ICELAKE: case PMC_CPU_INTEL_ICELAKE_XEON: + case PMC_CPU_INTEL_ALDERLAKE: default: break; } diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c index 2d8377e1a838..f59b7b41ece9 100644 --- a/sys/dev/hwpmc/hwpmc_intel.c +++ b/sys/dev/hwpmc/hwpmc_intel.c @@ -163,6 +163,27 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; + case 0x3D: + case 0x47: + cputype = PMC_CPU_INTEL_BROADWELL; + nclasses = 3; + break; + case 0x4f: + case 0x56: + cputype = PMC_CPU_INTEL_BROADWELL_XEON; + nclasses = 3; + break; + case 0x3C: /* Per Intel document 325462-045US 01/2013. */ + case 0x45: /* Per Intel document 325462-045US 09/2014. */ + cputype = PMC_CPU_INTEL_HASWELL; + nclasses = 3; + break; + case 0x3F: /* Per Intel document 325462-045US 09/2014. */ + case 0x46: /* Per Intel document 325462-045US 09/2014. */ + /* Should 46 be XEON. probably its own? */ + cputype = PMC_CPU_INTEL_HASWELL_XEON; + nclasses = 3; + break; /* Skylake */ case 0x4e: case 0x5e: @@ -195,25 +216,9 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_ICELAKE_XEON; nclasses = 3; break; - case 0x3D: - case 0x47: - cputype = PMC_CPU_INTEL_BROADWELL; - nclasses = 3; - break; - case 0x4f: - case 0x56: - cputype = PMC_CPU_INTEL_BROADWELL_XEON; - nclasses = 3; - break; - case 0x3F: /* Per Intel document 325462-045US 09/2014. */ - case 0x46: /* Per Intel document 325462-045US 09/2014. */ - /* Should 46 be XEON. probably its own? */ - cputype = PMC_CPU_INTEL_HASWELL_XEON; - nclasses = 3; - break; - case 0x3C: /* Per Intel document 325462-045US 01/2013. */ - case 0x45: /* Per Intel document 325462-045US 09/2014. */ - cputype = PMC_CPU_INTEL_HASWELL; + case 0x97: + case 0x9A: + cputype = PMC_CPU_INTEL_ALDERLAKE; nclasses = 3; break; case 0x37: @@ -250,40 +255,9 @@ pmc_intel_initialize(void) error = pmc_tsc_initialize(pmc_mdep, ncpus); if (error) goto error; - switch (cputype) { - /* - * Intel Core, Core 2 and Atom processors. - */ - case PMC_CPU_INTEL_ATOM: - case PMC_CPU_INTEL_ATOM_SILVERMONT: - case PMC_CPU_INTEL_ATOM_GOLDMONT: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_CORE: - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - case PMC_CPU_INTEL_COREI7: - case PMC_CPU_INTEL_NEHALEM_EX: - case PMC_CPU_INTEL_IVYBRIDGE: - case PMC_CPU_INTEL_SANDYBRIDGE: - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - case PMC_CPU_INTEL_HASWELL: - case PMC_CPU_INTEL_HASWELL_XEON: - MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF); - error = pmc_core_initialize(pmc_mdep, ncpus, verov); - break; - - default: - KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); - } + MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF); + error = pmc_core_initialize(pmc_mdep, ncpus, verov); if (error) { pmc_tsc_finalize(pmc_mdep); goto error; @@ -338,34 +312,7 @@ pmc_intel_finalize(struct pmc_mdep *md) { pmc_tsc_finalize(md); - switch (md->pmd_cputype) { - case PMC_CPU_INTEL_ATOM: - case PMC_CPU_INTEL_ATOM_SILVERMONT: - case PMC_CPU_INTEL_ATOM_GOLDMONT: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_CORE: - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - case PMC_CPU_INTEL_COREI7: - case PMC_CPU_INTEL_NEHALEM_EX: - case PMC_CPU_INTEL_HASWELL: - case PMC_CPU_INTEL_HASWELL_XEON: - case PMC_CPU_INTEL_IVYBRIDGE: - case PMC_CPU_INTEL_SANDYBRIDGE: - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - pmc_core_finalize(md); - break; - default: - KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); - } + pmc_core_finalize(md); /* * Uncore. diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index b54bc8d8e9f0..b84044ea5c6c 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -113,6 +113,7 @@ extern char pmc_cpuid[PMC_CPUID_LEN]; __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ + __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \