git: 0e19a22dd145 - stable/13 - arm64: Add explicit barrier after address translation instruction

The branch stable/13 has been updated by scottph:

URL: https://cgit.FreeBSD.org/src/commit/?id=0e19a22dd145c3e508978500a3b78592c84db5d0

commit 0e19a22dd145c3e508978500a3b78592c84db5d0
Author:     D Scott Phillips <scottph@FreeBSD.org>
AuthorDate: 2022-03-25 16:04:47 +0000
Commit:     D Scott Phillips <scottph@FreeBSD.org>
CommitDate: 2022-03-29 15:47:44 +0000

    arm64: Add explicit barrier after address translation instruction
    
    Following ARMARM sec D5.2.11, which says:
    
    > Where an instruction results in an update to a System register,
    > as is the case with the AT * address translation instructions,
    > explicit synchronization must be performed before the result is
    > guaranteed to be visible to subsequent direct reads of the
    > PAR_EL1.
    
    Reviewed By:    andrew
    MFC after:      3 weeks
    Sponsored by:   Ampere Computing
    Differential Revision:  https://reviews.freebsd.org/D34665
    
    (cherry picked from commit 7be7bd67758520ea2f9784a81ad244e99a7632f0)
---
 sys/arm64/include/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/include/cpu.h b/sys/arm64/include/cpu.h
index c926372a0ec6..b37301c276ce 100644
--- a/sys/arm64/include/cpu.h
+++ b/sys/arm64/include/cpu.h
@@ -198,7 +198,8 @@ arm64_address_translate_ ##stage (uint64_t addr)		\
 	uint64_t ret;						\
 								\
 	__asm __volatile(					\
-	    "at " __STRING(stage) ", %1 \n"					\
+	    "at " __STRING(stage) ", %1 \n"			\
+	    "isb \n"						\
 	    "mrs %0, par_el1" : "=r"(ret) : "r"(addr));		\
 								\
 	return (ret);						\