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Tue, 19 Jul 2022 07:37:24 GMT (envelope-from git) Date: Tue, 19 Jul 2022 07:37:24 GMT Message-Id: <202207190737.26J7bO9c021555@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: e444a9ba5ca3 - stable/13 - Add the SVE reigster definitions List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: e444a9ba5ca351fdb7540040110fbf5d1a789c2a Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1658216244; 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mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=e444a9ba5ca351fdb7540040110fbf5d1a789c2a commit e444a9ba5ca351fdb7540040110fbf5d1a789c2a Author: Andrew Turner AuthorDate: 2022-06-24 11:51:26 +0000 Commit: Andrew Turner CommitDate: 2022-07-19 07:03:30 +0000 Add the SVE reigster definitions Sponsored by: The FreeBSD Foundation (cherry picked from commit 2f317e7312971812bde8b8b0d9da21a2c1d378a3) --- sys/arm64/include/armreg.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index c164ebe9ece6..3753d550a256 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -108,6 +108,11 @@ #define CNTP_CTL_ISTATUS (1 << 2) /* CPACR_EL1 */ +#define CPACR_ZEN_MASK (0x3 << 16) +#define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ +#define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ +#define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ +#define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ #define CPACR_FPEN_MASK (0x3 << 20) #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ @@ -1503,4 +1508,9 @@ #define TTBR_CnP_SHIFT 0 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) +/* ZCR_EL1 - SVE Control Register */ +#define ZCR_LEN_SHIFT 0 +#define ZCR_LEN_MASK (0xf << ZCR_LEN_SHIFT) +#define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) + #endif /* !_MACHINE_ARMREG_H_ */