From nobody Mon Jan 10 12:02:34 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 359B2193A520; Mon, 10 Jan 2022 12:02:35 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4JXXWZ5xwHz4YcS; Mon, 10 Jan 2022 12:02:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id AC7D824D55; Mon, 10 Jan 2022 12:02:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 20AC2YWV079439; Mon, 10 Jan 2022 12:02:34 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 20AC2YMr079438; Mon, 10 Jan 2022 12:02:34 GMT (envelope-from git) Date: Mon, 10 Jan 2022 12:02:34 GMT Message-Id: <202201101202.20AC2YMr079438@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 77402d2834e6 - main - Move instructions into the arm64 exception vectors List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 77402d2834e64a3530fbaa47d57eccce23c58603 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1641816154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=u6XqRYucs3Dlx3cxJkaBPHkK7EDwxJiEHnBDImeQsec=; b=Kl3jikpQvc93fN+KYj7UNxz4A75W91NB4qCdTknMSpNBWTMMMIyJPQad79fE19DpOl8cT/ pEZNSa1FvWI5LdKJLlH1oBVvbTW2pFz9MJJ77S03vvM91jemQyLPFzyhvRTd1tgx+5xYpb nhmvUYYNVYmlBr93gcF8W95ew8USfnxYKMUnu24wcKkn4uaqqf4Vu+/SpZ6FDmxAvcvy2n ykVlJ14pywvrxJy51ST4Hl4IaMp8qK/unU9UJFiVQV3zNdS/xLrs6fbST61PFHTzyIiSaW ds+pzdXzMmWEnseVwnHrlVCknOncn3Wm+qzSpNl8Fke2GuQA+sD6B20FUbltOA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1641816154; a=rsa-sha256; cv=none; b=N4cRxZeNmlOZLTXq7kkP37fvbvoCg3VhrJqB34xvYdWGow1Sec/JNMQbtcCIOGK2zVd2E9 K3ZBtcNm7CpLB276iodmo8KdR73yH+EVki8sdmMhYQHlF1cpl2z7Nmi0UT0XDwEe9lXvmj Y3cnDXQy5iBNBVpIVab66WcSRu4PeTi0lhDcsm9Hm/WmRrXD4K/MEeEWIMDuuA8YwdZ1If K/5j2L5f5g9IyG9lwEqCfhKoS6FjAdsMh6SnED2Jbttaw8hLP0MBGDdXHaPBMv5U0WNmhX HGWVAsuXHTw6vjJ6uTW1Y8fmzr+6TTSr4VLFNflaUhaVj/qEXYXKlJYonDgZrA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=77402d2834e64a3530fbaa47d57eccce23c58603 commit 77402d2834e64a3530fbaa47d57eccce23c58603 Author: Andrew Turner AuthorDate: 2022-01-05 15:12:01 +0000 Commit: Andrew Turner CommitDate: 2022-01-10 10:51:16 +0000 Move instructions into the arm64 exception vectors We have 32 instructions in each exception vector on arm64. Previously only one was used to branch to the handler function. We can split the start of these functions and move some of the instructions into the vectors. Reviewed by: kib, markj Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D33751 --- sys/arm64/arm64/exception.S | 56 +++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S index d81bbce0efc7..afde9e7eb651 100644 --- a/sys/arm64/arm64/exception.S +++ b/sys/arm64/arm64/exception.S @@ -33,7 +33,12 @@ __FBSDID("$FreeBSD$"); .text -.macro save_registers el +/* + * This is limited to 28 instructions as it's placed in the exception vector + * slot that is 32 instructions long. We need one for the branch, and three + * for the prolog. + */ +.macro save_registers_head el .if \el == 1 mov x18, sp sub sp, sp, #128 @@ -65,6 +70,9 @@ __FBSDID("$FreeBSD$"); stp x18, lr, [sp, #(TF_SP)] mrs x18, tpidr_el1 add x29, sp, #(TF_SIZE) +.endm + +.macro save_registers el .if \el == 0 #if defined(PERTHREAD_SSP) /* Load the SSP canary to sp_el0 */ @@ -234,36 +242,40 @@ ENTRY(handle_empty_exception) b 1b END(handle_empty_exception) -.macro vempty +.macro vector name, el .align 7 - b handle_empty_exception + save_registers_head \el + b handle_\name + dsb sy + isb + /* Break instruction to ensure we aren't executing code here. */ + brk 0x42 .endm -.macro vector name - .align 7 - b handle_\name +.macro vempty el + vector empty_exception \el .endm .align 11 .globl exception_vectors exception_vectors: - vempty /* Synchronous EL1t */ - vempty /* IRQ EL1t */ - vempty /* FIQ EL1t */ - vempty /* Error EL1t */ + vempty 1 /* Synchronous EL1t */ + vempty 1 /* IRQ EL1t */ + vempty 1 /* FIQ EL1t */ + vempty 1 /* Error EL1t */ - vector el1h_sync /* Synchronous EL1h */ - vector el1h_irq /* IRQ EL1h */ - vempty /* FIQ EL1h */ - vector serror /* Error EL1h */ + vector el1h_sync 1 /* Synchronous EL1h */ + vector el1h_irq 1 /* IRQ EL1h */ + vempty 1 /* FIQ EL1h */ + vector serror 1 /* Error EL1h */ - vector el0_sync /* Synchronous 64-bit EL0 */ - vector el0_irq /* IRQ 64-bit EL0 */ - vempty /* FIQ 64-bit EL0 */ - vector serror /* Error 64-bit EL0 */ + vector el0_sync 0 /* Synchronous 64-bit EL0 */ + vector el0_irq 0 /* IRQ 64-bit EL0 */ + vempty 0 /* FIQ 64-bit EL0 */ + vector serror 0 /* Error 64-bit EL0 */ - vector el0_sync /* Synchronous 32-bit EL0 */ - vector el0_irq /* IRQ 32-bit EL0 */ - vempty /* FIQ 32-bit EL0 */ - vector serror /* Error 32-bit EL0 */ + vector el0_sync 0 /* Synchronous 32-bit EL0 */ + vector el0_irq 0 /* IRQ 32-bit EL0 */ + vempty 0 /* FIQ 32-bit EL0 */ + vector serror 0 /* Error 32-bit EL0 */