git: c6b711306082 - main - cad/verilator: update 5.028 → 5.030

The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=c6b711306082ec921f43e2659e3dd89e7f66d775

commit c6b711306082ec921f43e2659e3dd89e7f66d775
Author:     Yuri Victorovich <yuri@FreeBSD.org>
AuthorDate: 2024-10-28 19:05:54 +0000
Commit:     Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2024-10-28 19:06:21 +0000

    cad/verilator: update 5.028 → 5.030
    
    Reported by:    portscout
---
 cad/verilator/Makefile | 7 ++++---
 cad/verilator/distinfo | 6 +++---
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index c346ee9fe055..dd27f3b3509a 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,11 +1,12 @@
 PORTNAME=	verilator
 DISTVERSIONPREFIX=	v
-DISTVERSION=	5.028
+DISTVERSION=	5.030
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	Synthesizable Verilog to C++ compiler
-WWW=		https://www.veripool.org/projects/verilator/wiki/Intro
+WWW=		https://www.veripool.org/verilator/ \
+		https://github.com/verilator/verilator
 
 LICENSE=	GPLv3
 LICENSE_FILE=	${WRKSRC}/LICENSE
@@ -64,7 +65,7 @@ pre-configure:
 		autoconf
 
 post-install:
-	@${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/verilator/bin/verilator_bin
+	@${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/verilator_bin
 
 post-install-INSTALL_DBG_EXECUTABLES-on:
 	@${STRIP_CMD} \
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index 9662da6d7118..a16210d88b90 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1724606521
-SHA256 (verilator-verilator-v5.028_GH0.tar.gz) = 02d4b6f34754b46a97cfd70f5fcbc9b730bd1f0a24c3fc37223397778fcb142c
-SIZE (verilator-verilator-v5.028_GH0.tar.gz) = 32547892
+TIMESTAMP = 1730089848
+SHA256 (verilator-verilator-v5.030_GH0.tar.gz) = b9e7e97257ca3825fcc75acbed792b03c3ec411d6808ad209d20917705407eac
+SIZE (verilator-verilator-v5.030_GH0.tar.gz) = 32546625