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ESMTPS id 4Nc1Q6434lzhCF; Tue, 20 Dec 2022 15:55:58 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 2BKFtwCQ077656; Tue, 20 Dec 2022 15:55:58 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 2BKFtwAD077655; Tue, 20 Dec 2022 15:55:58 GMT (envelope-from git) Date: Tue, 20 Dec 2022 15:55:58 GMT Message-Id: <202212201555.2BKFtwAD077655@gitrepo.freebsd.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org From: Emmanuel Vadot Subject: git: 2d5b20aa4a87 - main - devel/trellis: Unbreak and update to g2022100712 List-Id: Commits to the main branch of the FreeBSD ports repository List-Archive: https://lists.freebsd.org/archives/dev-commits-ports-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-ports-main@freebsd.org X-BeenThere: dev-commits-ports-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: manu X-Git-Repository: ports X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 2d5b20aa4a87d7c3f5367c612095530ecc9ad8e8 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by manu: URL: https://cgit.FreeBSD.org/ports/commit/?id=2d5b20aa4a87d7c3f5367c612095530ecc9ad8e8 commit 2d5b20aa4a87d7c3f5367c612095530ecc9ad8e8 Author: Emmanuel Vadot AuthorDate: 2022-12-20 08:37:23 +0000 Commit: Emmanuel Vadot CommitDate: 2022-12-20 15:53:34 +0000 devel/trellis: Unbreak and update to g2022100712 --- devel/trellis/Makefile | 17 +-- devel/trellis/distinfo | 12 +- .../trellis/files/patch-libtrellis_CMakeLists.txt | 11 -- devel/trellis/pkg-plist | 168 ++++++++++++++++++++- 4 files changed, 177 insertions(+), 31 deletions(-) diff --git a/devel/trellis/Makefile b/devel/trellis/Makefile index e4406de7fd86..ef4aad6ef5fc 100644 --- a/devel/trellis/Makefile +++ b/devel/trellis/Makefile @@ -1,15 +1,10 @@ PORTNAME= trellis -PORTVERSION= g20190422 -PORTREVISION= 4 +PORTVERSION= g2022100712 CATEGORIES= devel -# Add Python 3.8 to search list in ${WRKSRC}/libtrellis/CMakeLists.txt -PATCH_SITES= https://github.com/${GH_ACCOUNT}/${GH_PROJECT}/commit/ -PATCHFILES= 2784291454a0307cf131acb5f0f68acc1eb4ffc3.patch:-p1 - MAINTAINER= manu@FreeBSD.Org COMMENT= Documenting the Lattice ECP5 bit-stream format -WWW= https://github.com/SymbiFlow/prjtrellis +WWW= https://github.com/YosysHQ/prjtrellis LICENSE= ISCL LICENSE_FILE= ${WRKSRC}/COPYING @@ -23,8 +18,6 @@ LIB_DEPENDS= libftdi1.so:devel/libftdi1 \ ${PY_BOOST} \ libboost_thread.so:devel/boost-libs -BROKEN= cannot find Boost-Python - USES= compiler:c++14-lang cmake python:3.5+ shebangfix SHEBANG_FILES= ${WRKSRC}/timing/util/cell_html.py \ @@ -33,10 +26,10 @@ SHEBANG_FILES= ${WRKSRC}/timing/util/cell_html.py \ USE_LDCONFIG= yes USE_GITHUB= yes -GH_ACCOUNT= SymbiFlow +GH_ACCOUNT= YosysHQ GH_PROJECT= prjtrellis -GH_TAGNAME= 5eb0ad87 -GH_TUPLE= SymbiFlow:prjtrellis-db:d0b219af:database/database +GH_TAGNAME= 35f5affe10 +GH_TUPLE= YosysHQ:prjtrellis-db:35d900a94ff:database/database CMAKE_SOURCE_PATH= ${WRKSRC}/libtrellis diff --git a/devel/trellis/distinfo b/devel/trellis/distinfo index 6d1b27d064b3..623511f0c8c4 100644 --- a/devel/trellis/distinfo +++ b/devel/trellis/distinfo @@ -1,7 +1,5 @@ -TIMESTAMP = 1615486005 -SHA256 (SymbiFlow-prjtrellis-g20190422-5eb0ad87_GH0.tar.gz) = e9611f0d3516048acd49e8f2228d13775a7fff14e41a8cb92c0e01918b3c10ff -SIZE (SymbiFlow-prjtrellis-g20190422-5eb0ad87_GH0.tar.gz) = 359933 -SHA256 (SymbiFlow-prjtrellis-db-d0b219af_GH0.tar.gz) = 88c94d6bf74f4156f07bf09f8c207f6e237e2583cca655ffd1e0ce3afd89dc16 -SIZE (SymbiFlow-prjtrellis-db-d0b219af_GH0.tar.gz) = 2361070 -SHA256 (2784291454a0307cf131acb5f0f68acc1eb4ffc3.patch) = 39ec4912e76076c8b010f17288bf37587398de24c7ba34b8c009af61645181f2 -SIZE (2784291454a0307cf131acb5f0f68acc1eb4ffc3.patch) = 1718 +TIMESTAMP = 1671546592 +SHA256 (YosysHQ-prjtrellis-g2022100712-35f5affe10_GH0.tar.gz) = 051610533a83e1236c02e563c4590e66b118e7843b7a0a5210e1edc6f32e06f7 +SIZE (YosysHQ-prjtrellis-g2022100712-35f5affe10_GH0.tar.gz) = 1157407 +SHA256 (YosysHQ-prjtrellis-db-35d900a94ff_GH0.tar.gz) = e4654ccf33cde0d9f386483688351e6318d4a7db2691a1eea4ccae7813f551b1 +SIZE (YosysHQ-prjtrellis-db-35d900a94ff_GH0.tar.gz) = 2909007 diff --git a/devel/trellis/files/patch-libtrellis_CMakeLists.txt b/devel/trellis/files/patch-libtrellis_CMakeLists.txt deleted file mode 100644 index b7fe3efc186c..000000000000 --- a/devel/trellis/files/patch-libtrellis_CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ ---- libtrellis/CMakeLists.txt.orig 2019-06-03 10:33:16 UTC -+++ libtrellis/CMakeLists.txt -@@ -109,7 +109,7 @@ endif() - find_package(Boost REQUIRED COMPONENTS program_options) - - get_property(LIB64 GLOBAL PROPERTY FIND_LIBRARY_USE_LIB64_PATHS) --if (NOT APPLE AND "${LIB64}" STREQUAL "TRUE") -+if (NOT APPLE AND "${LIB64}" STREQUAL "TRUE" AND NOT "${CMAKE_SYSTEM_NAME}" STREQUAL "FreeBSD") - set(LIBDIR "lib64") - else() - set(LIBDIR "lib") diff --git a/devel/trellis/pkg-plist b/devel/trellis/pkg-plist index e00d1dc360f6..4600e0dfe3c2 100644 --- a/devel/trellis/pkg-plist +++ b/devel/trellis/pkg-plist @@ -1,3 +1,4 @@ +bin/ecpbram bin/ecpmulti bin/ecppack bin/ecppll @@ -6,6 +7,9 @@ lib/trellis/libtrellis.so lib/trellis/pytrellis.so %%DATADIR%%/database/.gitignore %%DATADIR%%/database/COPYING +%%DATADIR%%/database/ECP5/LFE5U-12F/globals.json +%%DATADIR%%/database/ECP5/LFE5U-12F/iodb.json +%%DATADIR%%/database/ECP5/LFE5U-12F/tilegrid.json %%DATADIR%%/database/ECP5/LFE5U-25F/globals.json %%DATADIR%%/database/ECP5/LFE5U-25F/iodb.json %%DATADIR%%/database/ECP5/LFE5U-25F/tilegrid.json @@ -226,6 +230,161 @@ lib/trellis/pytrellis.so %%DATADIR%%/database/ECP5/timing/speed_8/interconnect.json %%DATADIR%%/database/ECP5/timing/speed_8_5G/cells.json %%DATADIR%%/database/ECP5/timing/speed_8_5G/interconnect.json +%%DATADIR%%/database/MachXO2/LCMXO2-1200HC/globals.json +%%DATADIR%%/database/MachXO2/LCMXO2-1200HC/iodb.json +%%DATADIR%%/database/MachXO2/LCMXO2-1200HC/tilegrid.json +%%DATADIR%%/database/MachXO2/LCMXO2-2000HC/globals.json +%%DATADIR%%/database/MachXO2/LCMXO2-2000HC/tilegrid.json +%%DATADIR%%/database/MachXO2/LCMXO2-256HC/globals.json +%%DATADIR%%/database/MachXO2/LCMXO2-256HC/tilegrid.json +%%DATADIR%%/database/MachXO2/LCMXO2-4000HC/globals.json +%%DATADIR%%/database/MachXO2/LCMXO2-4000HC/tilegrid.json +%%DATADIR%%/database/MachXO2/LCMXO2-640HC/globals.json +%%DATADIR%%/database/MachXO2/LCMXO2-640HC/tilegrid.json +%%DATADIR%%/database/MachXO2/LCMXO2-7000HC/globals.json +%%DATADIR%%/database/MachXO2/LCMXO2-7000HC/tilegrid.json +%%DATADIR%%/database/MachXO2/tiledata/B_DUMMY_ENDL/bits.db +%%DATADIR%%/database/MachXO2/tiledata/B_DUMMY_ENDR/bits.db +%%DATADIR%%/database/MachXO2/tiledata/B_DUMMY_ENDR_VREF2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER4/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER4_640/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER5/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER6/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER7/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER8/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTERB/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTERC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_B/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_B_CIB/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_B_CIB_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_EBR/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_EBR_CIB/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_EBR_CIB_4K/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_EBR_CIB_SP/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_EBR_SP/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_T/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_T_CIB/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CENTER_T_CIB_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CFG0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CFG0_ENDL/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CFG1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CFG2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CFG3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CIB_CFG0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CIB_CFG1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CIB_CFG2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CIB_CFG3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/CIB_EBR0/bits.db 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+%%DATADIR%%/database/MachXO2/tiledata/EBR2_640/bits.db +%%DATADIR%%/database/MachXO2/tiledata/EBR2_640_END/bits.db +%%DATADIR%%/database/MachXO2/tiledata/EBR2_END/bits.db +%%DATADIR%%/database/MachXO2/tiledata/EBR_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/EBR_DUMMY_END/bits.db +%%DATADIR%%/database/MachXO2/tiledata/GPLL_L0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/GPLL_R0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LLC0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LLC0PIC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LLC1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LLC1PIC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LLC2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LLC3PIC_VREF3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LRC0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LRC0PIC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LRC1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LRC1PIC1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/LRC1PIC2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_B0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_B0_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_BS0_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_B_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_B_DUMMY_VIQ/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_B_DUMMY_VIQ_VREF/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_B_DUMMY_VREF/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L0_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L0_DUMMY_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L0_VREF3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L1_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L1_DUMMY_640/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L1_VREF3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L1_VREF4/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L1_VREF5/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L2_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L2_VREF4/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L2_VREF5/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L3/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L3_VREF4/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_L3_VREF5/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_LS0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R0_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R0_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R0_DUMMY_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R1_640/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R1_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_R1_DUMMY_640/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_RS0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_RS0_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_T0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_T0_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_TS0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_T_DUMMY/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_T_DUMMY_OSC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_T_DUMMY_VIQ/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PIC_T_DUMMY_VIQ_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/PLC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/T_DUMMY_ENDR/bits.db +%%DATADIR%%/database/MachXO2/tiledata/ULC0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/ULC0_256/bits.db +%%DATADIR%%/database/MachXO2/tiledata/ULC1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/ULC1_640/bits.db +%%DATADIR%%/database/MachXO2/tiledata/ULC2/bits.db +%%DATADIR%%/database/MachXO2/tiledata/ULC3PIC/bits.db +%%DATADIR%%/database/MachXO2/tiledata/URC0/bits.db +%%DATADIR%%/database/MachXO2/tiledata/URC0VREF/bits.db +%%DATADIR%%/database/MachXO2/tiledata/URC1/bits.db +%%DATADIR%%/database/MachXO2/tiledata/URC1PIC/bits.db %%DATADIR%%/database/README.md %%DATADIR%%/database/devices.json %%DATADIR%%/misc/basecfgs/README.md @@ -238,9 +397,11 @@ lib/trellis/pytrellis.so %%DATADIR%%/misc/basecfgs/empty_lfe5um5g-25f.config %%DATADIR%%/misc/basecfgs/empty_lfe5um5g-45f.config %%DATADIR%%/misc/basecfgs/empty_lfe5um5g-85f.config +%%DATADIR%%/misc/basecfgs/empty_machxo2-1200hc.config %%DATADIR%%/misc/openocd/ecp5-evn.cfg %%DATADIR%%/misc/openocd/ecp5-versa.cfg %%DATADIR%%/misc/openocd/ecp5-versa5g.cfg +%%DATADIR%%/misc/openocd/trellisboard.cfg %%DATADIR%%/misc/openocd/ulx3s.cfg %%DATADIR%%/misc/openocd/ulx3s_85k.cfg %%DATADIR%%/timing/util/.gitignore @@ -260,5 +421,10 @@ lib/trellis/pytrellis.so %%DATADIR%%/util/common/devices.py %%DATADIR%%/util/common/diamond.py %%DATADIR%%/util/common/isptcl.py -%%DATADIR%%/util/common/nets.py +%%DATADIR%%/util/common/nets/__init__.py +%%DATADIR%%/util/common/nets/__main__.py +%%DATADIR%%/util/common/nets/ecp5.py +%%DATADIR%%/util/common/nets/general.py +%%DATADIR%%/util/common/nets/machxo2.py +%%DATADIR%%/util/common/nets/util.py %%DATADIR%%/util/common/tiles.py