From nobody Tue Mar 21 19:23:54 2023 X-Original-To: dev-commits-ports-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Ph1k30yYTz40ghP; Tue, 21 Mar 2023 19:23:55 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Ph1k302Mjz4B6M; Tue, 21 Mar 2023 19:23:55 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1679426635; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ld3V4L4nlx4khR3NWcJL7OoMEhKEEkMROt9JmjXk/6Y=; b=QP2XPApIoo7AJg7EJ/zTS46SmCHIA/m2q17f8y034TZSjrGnPLd//OpG+NUkvKF+0g63Bx SugtI/vXPVnuIS08REyXuuN/PnNEummBhcb0/JnuuH9r0HOvfBbZ+xDKAYOnpGI8ZWhE3W 4bnbJRPYqWTJAlf2sgPQEl5s0LRv1+SEysXAGN9vmFpFH2tsVQETm8sFayGQBGDXuYOxp8 SWXMeHn92UTEHyfGnuCNwCxfLI+Gmz4ZVZgT0n5nDi/+Z85WyM0C1Ez76sAWjMnJ1ZgrPE NWZKhISnURowbAuny9sRrLSa+Cs3fNeaI+cU5jh/ecc/QSOYD9yHbfoM1Dgzhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1679426635; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ld3V4L4nlx4khR3NWcJL7OoMEhKEEkMROt9JmjXk/6Y=; b=rlY8qM9BlZ7rXQ/oTm1TJ62Tn4dJ4o8Ks1sV24pcrmIBE3ZnyvUbgPQGUOYUkcewinTgfJ lbCcVHxV7L/PX4YEOL+8aQwPkEa6x/aGJQWd7NjBq+NNh+otPOGzOh+xULvjD9skNcV96q RYZqk/iO8FcD+hPzAA+pd2a8ONrsqEK3z0wVnWVsxqNLu+sqpynQPWZo80aXqJxtnIMzzR EOzXyTrVPsyBNlj/bL4Y1JqA2I9HGqjSXyLaIIDe14kpNeJ5PeEDSXZjar+qc0dRoJy9Bb wxQHva5Lw6yv/seDOkRjYnRl9L0P0aWWPvAYFxGnBWw7PW4f2GEQCWpUXkefaA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1679426635; a=rsa-sha256; cv=none; b=nlOn4XDfP4mFb9PoDkMNyV/05NcF/iVq0AWir9dvswBmDLetvaNeJuOjN96S3AAgVX065V 4k4jWO/vwbgmgMncKAr8yNvX2na/CGMh0OR7iEk3mBZqCvIe579+etRv5S5MVplMWaDS1e ORj5AGarCs8Xn78K/i9Gsf3Ns2E40hwnVt7OYu3R4PIQU0YU/4Ca4cv39QVkz4lhVrv3H2 tyseQkISA3xkxbKMrvl/VAH4J6HwN3+02gpbhhIxc0LqEE2dsrkQ3RB7WTMhRpvXgbwTiZ FI8UemP/x5rF5u8UAiYrMA2cLtJsfwXs8KWMUljZinQJ5LkvECwVjRP8ViQbfQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4Ph1k267rQzPM4; Tue, 21 Mar 2023 19:23:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 32LJNsA1026930; Tue, 21 Mar 2023 19:23:54 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 32LJNsA1026929; Tue, 21 Mar 2023 19:23:54 GMT (envelope-from git) Date: Tue, 21 Mar 2023 19:23:54 GMT Message-Id: <202303211923.32LJNsA1026929@gitrepo.freebsd.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-branches@FreeBSD.org From: Matthias Andree Subject: git: b7e05a72e644 - 2023Q1 - graphics/openexr: Fix ARMv7 build List-Id: Commits to the quarterly branches of the FreeBSD ports repository List-Archive: https://lists.freebsd.org/archives/dev-commits-ports-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-ports-branches@freebsd.org X-BeenThere: dev-commits-ports-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mandree X-Git-Repository: ports X-Git-Refname: refs/heads/2023Q1 X-Git-Reftype: branch X-Git-Commit: b7e05a72e644249c32c2e723d015b7af444c8690 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch 2023Q1 has been updated by mandree: URL: https://cgit.FreeBSD.org/ports/commit/?id=b7e05a72e644249c32c2e723d015b7af444c8690 commit b7e05a72e644249c32c2e723d015b7af444c8690 Author: Matthias Andree AuthorDate: 2023-03-21 16:42:19 +0000 Commit: Matthias Andree CommitDate: 2023-03-21 19:22:30 +0000 graphics/openexr: Fix ARMv7 build OpenEXR 3.1.6 introduced several NEON-based optimizations that implied Aarch64. Add patched, either picked from upstream, or written by mandree@, to enable those NEON features that also require Aarch64 only there. PR-1366 is cherry-picked from upstream, and patch-lib/patch-test files are my work but build upon said PR. Also cherry-pick PR1354 that adds a missing check for AVX, which is why I am bumping PORTREVISION because it might change code (I have not checked). https://github.com/AcademySoftwareFoundation/openexr/issues/1365 PR: 270348 Reported by: fuz@ (Robert Clausecker) (cherry picked from commit 54d6860aac464b690f37007cfaef52c5a0b427b0) --- graphics/openexr/Makefile | 4 +- ...PR1354-3f97750d1ec203e7d7eb8d5f30f3d5e7e68ad720 | 25 ++++++ ...PR1366-a41a736d64e3d93baffef1042d4a3d1aaf74f1c9 | 98 ++++++++++++++++++++++ .../files/patch-lib_OpenEXR_ImfDwaCompressor.cpp | 11 +++ .../files/patch-lib_OpenEXR_ImfDwaCompressorSimd.h | 29 +++++++ ...atch-test_OpenEXRTest_testDwaCompressorSimd.cpp | 38 +++++++++ 6 files changed, 203 insertions(+), 2 deletions(-) diff --git a/graphics/openexr/Makefile b/graphics/openexr/Makefile index 87011420e1b1..26c735c4849f 100644 --- a/graphics/openexr/Makefile +++ b/graphics/openexr/Makefile @@ -1,6 +1,6 @@ PORTNAME= openexr PORTVERSION= 3.1.6 -PORTREVISION= 0 +PORTREVISION= 1 CATEGORIES= graphics devel MAINTAINER= mandree@FreeBSD.org @@ -23,7 +23,7 @@ CPPFLAGS+= -I. # must be linked with -l{thr|pthread} explicitly LDFLAGS+= -lpthread -PATCH_STRIP= -p0 +PATCH_STRIP= -p1 _MAJORVER= 3_1 _VER= 30 diff --git a/graphics/openexr/files/patch-PR1354-3f97750d1ec203e7d7eb8d5f30f3d5e7e68ad720 b/graphics/openexr/files/patch-PR1354-3f97750d1ec203e7d7eb8d5f30f3d5e7e68ad720 new file mode 100644 index 000000000000..edd1bb3ecc08 --- /dev/null +++ b/graphics/openexr/files/patch-PR1354-3f97750d1ec203e7d7eb8d5f30f3d5e7e68ad720 @@ -0,0 +1,25 @@ +From 3f97750d1ec203e7d7eb8d5f30f3d5e7e68ad720 Mon Sep 17 00:00:00 2001 +From: Cary Phillips +Date: Thu, 16 Mar 2023 07:23:18 -0700 +Subject: [PATCH] Test for AVC in unpack.c (#1354) + +Addresses #1353 + +Signed-off-by: Cary Phillips +--- + src/lib/OpenEXRCore/unpack.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/lib/OpenEXRCore/unpack.c b/src/lib/OpenEXRCore/unpack.c +index 606d7c3eb..ac4e259f3 100644 +--- a/src/lib/OpenEXRCore/unpack.c ++++ b/src/lib/OpenEXRCore/unpack.c +@@ -37,7 +37,7 @@ half_to_float8 (float* out, const uint16_t* src) + } + #endif + +-#if (defined(__x86_64__) || defined(_M_X64)) && \ ++#if (defined(__x86_64__) || defined(_M_X64)) && defined(__AVX__) && \ + (defined(__F16C__) || defined(__GNUC__) || defined(__clang__)) + + # if defined(__F16C__) diff --git a/graphics/openexr/files/patch-PR1366-a41a736d64e3d93baffef1042d4a3d1aaf74f1c9 b/graphics/openexr/files/patch-PR1366-a41a736d64e3d93baffef1042d4a3d1aaf74f1c9 new file mode 100644 index 000000000000..054dc785eec5 --- /dev/null +++ b/graphics/openexr/files/patch-PR1366-a41a736d64e3d93baffef1042d4a3d1aaf74f1c9 @@ -0,0 +1,98 @@ +From a41a736d64e3d93baffef1042d4a3d1aaf74f1c9 Mon Sep 17 00:00:00 2001 +From: Aras Pranckevicius +Date: Mon, 20 Mar 2023 19:31:42 +0200 +Subject: [PATCH] Fix ARMv7 build by making recent ZIP NEON optimizations be + ARMv8 (aarch64) only + +Should fix #1365. Recent PR (#1348) added NEON accelerated code paths +for ZIP filtering. But that code uses several instructions that are +ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) +platforms. Make these optimizations only kick in when building +for 64-bit ARM platforms. + +Signed-off-by: Aras Pranckevicius +--- + src/lib/OpenEXR/ImfSimd.h | 4 ++++ + src/lib/OpenEXR/ImfZip.cpp | 6 +++--- + src/lib/OpenEXRCore/internal_zip.c | 8 ++++---- + 3 files changed, 11 insertions(+), 7 deletions(-) + +diff --git a/src/lib/OpenEXR/ImfSimd.h b/src/lib/OpenEXR/ImfSimd.h +index 3053a5d4e..d1f064525 100644 +--- a/src/lib/OpenEXR/ImfSimd.h ++++ b/src/lib/OpenEXR/ImfSimd.h +@@ -46,6 +46,10 @@ + # define IMF_HAVE_NEON + #endif + ++#if defined(__aarch64__) ++# define IMF_HAVE_NEON_AARCH64 1 ++#endif ++ + extern "C" { + #ifdef IMF_HAVE_SSE2 + # include +diff --git a/src/lib/OpenEXR/ImfZip.cpp b/src/lib/OpenEXR/ImfZip.cpp +index 0e2b031d8..8dd53bea9 100644 +--- a/src/lib/OpenEXR/ImfZip.cpp ++++ b/src/lib/OpenEXR/ImfZip.cpp +@@ -160,7 +160,7 @@ reconstruct_sse41 (char* buf, size_t outSize) + + #endif + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + + void + reconstruct_neon (char* buf, size_t outSize) +@@ -262,7 +262,7 @@ interleave_sse2 (const char* source, size_t outSize, char* out) + + #endif + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + + void + interleave_neon (const char* source, size_t outSize, char* out) +@@ -380,7 +380,7 @@ Zip::initializeFuncs () + } + #endif + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + reconstruct = reconstruct_neon; + interleave = interleave_neon; + #endif +diff --git a/src/lib/OpenEXRCore/internal_zip.c b/src/lib/OpenEXRCore/internal_zip.c +index e829e6d7c..1374cab0d 100644 +--- a/src/lib/OpenEXRCore/internal_zip.c ++++ b/src/lib/OpenEXRCore/internal_zip.c +@@ -24,8 +24,8 @@ + # define IMF_HAVE_SSE4_1 1 + # include + #endif +-#if defined(__ARM_NEON) +-# define IMF_HAVE_NEON 1 ++#if defined(__aarch64__) ++# define IMF_HAVE_NEON_AARCH64 1 + # include + #endif + +@@ -78,7 +78,7 @@ reconstruct (uint8_t* buf, uint64_t outSize) + prev = d; + } + } +-#elif defined(IMF_HAVE_NEON) ++#elif defined(IMF_HAVE_NEON_AARCH64) + static void + reconstruct (uint8_t* buf, uint64_t outSize) + { +@@ -174,7 +174,7 @@ interleave (uint8_t* out, const uint8_t* source, uint64_t outSize) + *(sOut++) = (i % 2 == 0) ? *(t1++) : *(t2++); + } + +-#elif defined(IMF_HAVE_NEON) ++#elif defined(IMF_HAVE_NEON_AARCH64) + static void + interleave (uint8_t* out, const uint8_t* source, uint64_t outSize) + { diff --git a/graphics/openexr/files/patch-lib_OpenEXR_ImfDwaCompressor.cpp b/graphics/openexr/files/patch-lib_OpenEXR_ImfDwaCompressor.cpp new file mode 100644 index 000000000000..5b908fdad69e --- /dev/null +++ b/graphics/openexr/files/patch-lib_OpenEXR_ImfDwaCompressor.cpp @@ -0,0 +1,11 @@ +--- ./src/lib/OpenEXR/ImfDwaCompressor.cpp.orig 2023-03-05 20:23:47 UTC ++++ ./src/lib/OpenEXR/ImfDwaCompressor.cpp +@@ -2888,7 +2888,7 @@ DwaCompressor::initializeFuncs() + fromHalfZigZag = fromHalfZigZag_f16c; + } + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + { + convertFloatToHalf64 = convertFloatToHalf64_neon; + fromHalfZigZag = fromHalfZigZag_neon; diff --git a/graphics/openexr/files/patch-lib_OpenEXR_ImfDwaCompressorSimd.h b/graphics/openexr/files/patch-lib_OpenEXR_ImfDwaCompressorSimd.h new file mode 100644 index 000000000000..e9eff7e1a909 --- /dev/null +++ b/graphics/openexr/files/patch-lib_OpenEXR_ImfDwaCompressorSimd.h @@ -0,0 +1,29 @@ +--- ./src/lib/OpenEXR/ImfDwaCompressorSimd.h.orig 2023-03-05 20:23:47 UTC ++++ ./src/lib/OpenEXR/ImfDwaCompressorSimd.h +@@ -395,7 +395,7 @@ convertFloatToHalf64_scalar (unsigned short* dst, floa + dst[i] = ((half) src[i]).bits (); + } + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + + void + convertFloatToHalf64_neon (unsigned short* dst, float* src) +@@ -821,7 +821,7 @@ fromHalfZigZag_f16c (unsigned short* src, float* dst) + #endif /* defined IMF_HAVE_GCC_INLINEASM_X86_64 */ + } + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + + + void +@@ -856,7 +856,7 @@ fromHalfZigZag_neon(unsigned short* __restrict__ src, + } + } + +-#endif // IMF_HAVE_NEON ++#endif // IMF_HAVE_NEON_AARCH64 + + // + // Inverse 8x8 DCT, only inverting the DC. This assumes that diff --git a/graphics/openexr/files/patch-test_OpenEXRTest_testDwaCompressorSimd.cpp b/graphics/openexr/files/patch-test_OpenEXRTest_testDwaCompressorSimd.cpp new file mode 100644 index 000000000000..4d9991f463d3 --- /dev/null +++ b/graphics/openexr/files/patch-test_OpenEXRTest_testDwaCompressorSimd.cpp @@ -0,0 +1,38 @@ +--- ./src/test/OpenEXRTest/testDwaCompressorSimd.cpp.orig 2023-03-05 20:23:47 UTC ++++ ./src/test/OpenEXRTest/testDwaCompressorSimd.cpp +@@ -401,7 +401,7 @@ testFloatToHalf() + } + } + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + { + cout << " convertFloatToHalf64_neon()" << endl; + for (int iter = 0; iter < numIter; ++iter) +@@ -430,7 +430,7 @@ testFloatToHalf() + } + } + } +- #endif // IMF_HAVE_NEON ++ #endif // IMF_HAVE_NEON_AARCH64 + } + + // +@@ -516,7 +516,7 @@ testFromHalfZigZag() + } // iter + } // f16c + +-#ifdef IMF_HAVE_NEON ++#ifdef IMF_HAVE_NEON_AARCH64 + { + const int numIter = 1000000; + Rand48 rand48 (0); +@@ -553,7 +553,7 @@ testFromHalfZigZag() + } // iter + } // neon + +-#endif // IMF_HAVE_NEON ++#endif // IMF_HAVE_NEON_AARCH64 + } + +