git: 8914ed49e5dd - main - cad/yosys-systemverilog: Add PORTSCOUT tag

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From: Yuri Victorovich <yuri_at_FreeBSD.org>
Date: Mon, 19 Jun 2023 01:38:55 UTC

The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=8914ed49e5ddf883abaa88069e21b204f840f868

commit 8914ed49e5ddf883abaa88069e21b204f840f868
Author:     Yuri Victorovich <yuri@FreeBSD.org>
AuthorDate: 2023-06-18 21:35:36 +0000
Commit:     Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2023-06-19 01:38:52 +0000

    cad/yosys-systemverilog: Add PORTSCOUT tag
---
 cad/yosys-systemverilog/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cad/yosys-systemverilog/Makefile b/cad/yosys-systemverilog/Makefile
index 570dda2e41e5..8918269008c0 100644
--- a/cad/yosys-systemverilog/Makefile
+++ b/cad/yosys-systemverilog/Makefile
@@ -52,6 +52,8 @@ OPTIONS_DEFAULT=	TCMALLOC # should be the same TCMALLOC default as in cad/yosys,
 TCMALLOC_LDFLAGS=	`pkg-config --libs libtcmalloc`
 TCMALLOC_LIB_DEPENDS=	libtcmalloc.so:devel/google-perftools
 
+PORTSCOUT=	ignore:1 # until https://github.com/antmicro/yosys-systemverilog/issues/1798 is resolved
+
 post-extract:
 	@${CP} ${WRKSRC_yosys}/passes/pmgen/pmgen.py ${WRKSRC}/yosys-f4pga-plugins