git: 4949e8270ef5 - main - lang/silq: Fix build failures due to llvm13 changes

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From: Stefan Eßer <se_at_FreeBSD.org>
Date: Sat, 20 Nov 2021 19:39:30 UTC
The branch main has been updated by se:

URL: https://cgit.FreeBSD.org/ports/commit/?id=4949e8270ef54e5ae32f1ab66585ca0b55fc6235

commit 4949e8270ef54e5ae32f1ab66585ca0b55fc6235
Author:     Stefan Eßer <se@FreeBSD.org>
AuthorDate: 2021-11-20 19:39:02 +0000
Commit:     Stefan Eßer <se@FreeBSD.org>
CommitDate: 2021-11-20 19:39:02 +0000

    lang/silq: Fix build failures due to llvm13 changes
    
    The visibility rules of some variables have been changed in LLD13,
    leading to link failures.
    
    This is no issue if LDC is built with LLVM13, but the version
    currently in the ports tree  is too old to be build with LLVM13.
    
    As a work around and since the currently provided LDC is built with
    LLVM10, make this port depend on LLVM10, too.
    
    Update to the latest development source level on this occasion.
---
 lang/silq/Makefile  | 19 +++++++++++++------
 lang/silq/distinfo  | 14 +++++++-------
 lang/silq/pkg-plist | 18 ++++++++++++++++++
 3 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/lang/silq/Makefile b/lang/silq/Makefile
index ce8ce6bc9d27..2b493dfb814c 100644
--- a/lang/silq/Makefile
+++ b/lang/silq/Makefile
@@ -1,5 +1,5 @@
 PORTNAME=	silq
-PORTVERSION=	20210503
+PORTVERSION=	20211117
 CATEGORIES=	lang math science
 
 MAINTAINER=	se@FreeBSD.org
@@ -11,22 +11,29 @@ LICENSE_FILE=	${WRKSRC}/LICENSE
 ONLY_FOR_ARCHS=	amd64
 ONLY_FOR_ARCHS_REASON=	unknown status of the D language compiler (lang/ldc) on ${ARCH}
 
-BUILD_DEPENDS=	ldmd2:lang/ldc
+BUILD_DEPENDS=	ldmd2:lang/ldc \
+		llvm${LLVM_VERSION}>0:devel/llvm${LLVM_VERSION}
 
 USE_GITHUB=	yes
 
-GH_TUPLE=	eth-sri:silq:c0029ff \
-		tgehr:ast:cfa0289:ast/ast \
-		tgehr:util:eb42377:util/util
+GH_TUPLE=	eth-sri:silq:1bc7ece \
+		tgehr:ast:7c26e76:ast/ast \
+		tgehr:util:7e9f0ce:util/util
 
 OPTIONS_DEFINE=	EXAMPLES
 
+LLVM_VERSION=	10
+
+.include <bsd.port.options.mk>
+
 do-build:
-		cd ${WRKSRC}; ldmd2 -O -inline -J. -Jlibrary *.d ast/*.d util/*.d -linker=lld -of=silq
+		cd ${WRKSRC}; ldmd2 -O -inline -J. -Jlibrary *.d ast/*.d util/*.d -linker=lld${LLVM_VERSION} -of=silq
 
 do-install:
 		${INSTALL_PROGRAM} ${WRKSRC}/silq ${STAGEDIR}${PREFIX}/bin/
+.if ${PORT_OPTIONS:MEXAMPLES}
 		${MKDIR} ${STAGEDIR}${EXAMPLESDIR}
 		cd ${WRKSRC}/test && ${COPYTREE_SHARE} . ${STAGEDIR}${EXAMPLESDIR} "-name *\.slq"
+.endif
 
 .include <bsd.port.mk>
diff --git a/lang/silq/distinfo b/lang/silq/distinfo
index bdbf7bbb503f..d3344e178e18 100644
--- a/lang/silq/distinfo
+++ b/lang/silq/distinfo
@@ -1,7 +1,7 @@
-TIMESTAMP = 1620025724
-SHA256 (eth-sri-silq-20210503-c0029ff_GH0.tar.gz) = 3cc68bc91bd1d102fd153e50652280303a30a66cd188ab61287797674e06e032
-SIZE (eth-sri-silq-20210503-c0029ff_GH0.tar.gz) = 240778
-SHA256 (tgehr-ast-cfa0289_GH0.tar.gz) = 3fe66c32c761cfefb376db087d5d137bdcc5ce1f824d8f672c6fea139639e7ba
-SIZE (tgehr-ast-cfa0289_GH0.tar.gz) = 74430
-SHA256 (tgehr-util-eb42377_GH0.tar.gz) = 52dee367fb158d604cf80dff8b576adf61de0c34d7f0d4f9548f403049602ddd
-SIZE (tgehr-util-eb42377_GH0.tar.gz) = 9457
+TIMESTAMP = 1637153546
+SHA256 (eth-sri-silq-20211117-1bc7ece_GH0.tar.gz) = 9c51050b234373bb79762384cbd5556df6962fbb60e08e2e72e4e43556cdb639
+SIZE (eth-sri-silq-20211117-1bc7ece_GH0.tar.gz) = 242312
+SHA256 (tgehr-ast-7c26e76_GH0.tar.gz) = cd67b2e1ce6426ddfab4b0772b7c9812f4d3008293953f4420e06be4db2d2450
+SIZE (tgehr-ast-7c26e76_GH0.tar.gz) = 75083
+SHA256 (tgehr-util-7e9f0ce_GH0.tar.gz) = f73af612a6aa14c966cc46f392394d8c43b90ecf8c0be0c44b509cc07a7e949f
+SIZE (tgehr-util-7e9f0ce_GH0.tar.gz) = 9455
diff --git a/lang/silq/pkg-plist b/lang/silq/pkg-plist
index 1366c8a3ea51..f9fddea1b798 100644
--- a/lang/silq/pkg-plist
+++ b/lang/silq/pkg-plist
@@ -124,6 +124,7 @@ bin/silq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertMatch2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertNatToInt.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertTuple.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertVectors.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest3.slq
@@ -193,12 +194,14 @@ bin/silq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/grover2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/groverDiffusion.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/hIndex.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/hidingIndexReplacement.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifError.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifFalseReassign.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifSuperposition.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifSuperposition2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifSuperposition3.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/implicitDup.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/implicitDupLifted.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds3.slq
@@ -247,6 +250,7 @@ bin/silq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex3.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiReplace.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiResultIndexReplace.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mustConsumeNonLifted.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedClosure.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedGlobal.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedMeasure.slq
@@ -295,6 +299,14 @@ bin/silq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeat100.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeatUntil.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndex.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti0.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti1.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti2.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti3.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti4.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti5.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti6.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti7.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ret2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/retClosure.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/retPi.slq
@@ -319,6 +331,9 @@ bin/silq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotX.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotY.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotZ.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare1.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare2.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare3.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSubtype.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseToW.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseX.slq
@@ -334,11 +349,14 @@ bin/silq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/sumIota.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray2.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray3.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray4.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapClosures.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapDiffArrays.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapEmptyIf.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapInt.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent.slq
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent2.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/teleportation.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test.slq
 %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test3.slq