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Fri, 12 Jul 2024 14:29:30 GMT (envelope-from git) Date: Fri, 12 Jul 2024 14:29:30 GMT Message-Id: <202407121429.46CETUCp099628@gitrepo.freebsd.org> To: doc-committers@FreeBSD.org, dev-commits-doc-all@FreeBSD.org From: Mitchell Horne Subject: git: 6f80e223c1 - main - Status/2024q2/riscv.adoc: Add report List-Id: Commit messages for all branches of the doc repository List-Archive: https://lists.freebsd.org/archives/dev-commits-doc-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-doc-all@freebsd.org Sender: owner-dev-commits-doc-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: doc X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 6f80e223c1fccc8f8b52ab797bd550f0520ba0b1 Auto-Submitted: auto-generated The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/doc/commit/?id=6f80e223c1fccc8f8b52ab797bd550f0520ba0b1 commit 6f80e223c1fccc8f8b52ab797bd550f0520ba0b1 Author: Mitchell Horne AuthorDate: 2024-07-10 19:54:15 +0000 Commit: Mitchell Horne CommitDate: 2024-07-12 14:27:46 +0000 Status/2024q2/riscv.adoc: Add report Approved by: salvadore, Pau Amma Differential Revision: https://reviews.freebsd.org/D45948 --- .../en/status/report-2024-04-2024-06/riscv.adoc | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/website/content/en/status/report-2024-04-2024-06/riscv.adoc b/website/content/en/status/report-2024-04-2024-06/riscv.adoc new file mode 100644 index 0000000000..96b16f6347 --- /dev/null +++ b/website/content/en/status/report-2024-04-2024-06/riscv.adoc @@ -0,0 +1,71 @@ +=== FreeBSD/riscv64 + +Links: + +link:https://wiki.freebsd.org/riscv[Wiki Homepage] URL: link:https://wiki.freebsd.org/riscv[] + + +Contact: Mitchell Horne +Contact: Ruslan Bukin +Contact: Jari Sihvola + +The FreeBSD/RISC-V project is providing support for running FreeBSD on the link:https://riscv.org[RISC-V Instruction Set Architecture]. + +==== BSDCan Devsummit Updates + +Mitchell gave a presentation on the status of the FreeBSD/riscv64 platform at the June developers' summit, part of BSDCan 2024. +The presentation discussed the challenges of supporting the evolving RISC-V ISA, and gave a brief overview of some available hardware targets. +It is informal in nature, but available to watch on youtube. + +link:https://www.youtube.com/watch?v=O7zW7Z9U0ns[] + +==== StarFive JH7110 SoC / VisionFive v2 + +Work has been ongoing to support the JH7110 RISC-V SoC in FreeBSD. +This SoC is present in several existing RISC-V SBCs. +The primary support target is the VisionFive v2, but this work is likely to benefit similar hardware such as the Pine64 Star64 and the Milk-V Mars. + +At present, the support in CURRENT is partially complete. +What is working: + * UART + * clk/reset drivers + * MMC/SD + +The next target is working ethernet, which is supported with extensions to the `if_eqos` driver. +This code is functional, but still in review. + +Work on this has been performed by Jari, with review, testing, and integration from Mitchell. + +link:https://wiki.freebsd.org/riscv/StarFive[] + +==== T-HEAD/XuanTie CPU Support + +As discussed in the devsummit presentation, these CPUs present several barriers to support. +The problems come primarily from custom vendor extensions: non-coherent device I/O with custom cache management instructions, and a custom (spec-violating) implementation of page-based memory types. +Combined, these quirks require difficult and invasive changes to pmap, busdma, and early boot code. + +At the same time, we are seeing an increasing amount of available hardware based on this IP, and so support becomes a repeated question and incentive. + +Work on page-based memory types is underway and expected to land soon in CURRENT. +This feature allows individual virtual memory pages to be assigned specific properties, e.g. cacheability requirements. +The riscv64 pmap has been extended to support the official RISC-V 'Svpbmt' extension, and the T-HEAD version of PBMT. +These alternative encodings are incompatible, but provide similar functionality. + +Work on the device coherence and cache management challenges will begin next quarter. + +The hope is that this foundational work will (eventually) enable board support for available RISC-V hardware such as: + * Allwinner D1 (Nehza) + * Sipeed Lichee Pi 4A + * Beagle-V Ahead + * Milk-V Pioneer + +==== RISC-V Hypervisor + +Experimental support for the RISC-V hypervisor in bhyve/`vmm(4)` is under active development. +Currently, single-core VMs are possible, and the guest can boot to multi-user. + +Note: the "H" (hypervisor) extension is not implemented by any known existing or upcoming RISC-V hardware. +It is fully supported by software simulators such as Spike or QEMU. + +link:https://wiki.freebsd.org/riscv/bhyve[] + +Sponsor: The FreeBSD Foundation (mhorne's work) +Sponsor: UKRI (br's work)